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* [AMDGPU] Support for v3i32/v3f32Tim Renouf2019-03-211-5/+4
* [FileCheck] Add -allow-deprecated-dag-overlap to failing llvm testsJoel E. Denny2018-07-111-2/+2
* AMDGPU: Add pass to lower kernel arguments to loadsMatt Arsenault2018-06-261-72/+37
* AMDGPU: Make v4i16/v4f16 legalMatt Arsenault2018-06-151-25/+53
* AMDGPU: Try a lot harder to emit scalar loadsMatt Arsenault2018-06-071-59/+30
* AMDGPU: Switch some half using-tests to use amdhsaMatt Arsenault2018-06-011-107/+110
* AMDGPU: Use better alignment for kernarg loweringMatt Arsenault2018-05-301-23/+11
* AMDGPU: Make v2i16/v2f16 legal on VIMatt Arsenault2018-05-221-36/+68
* AMDGPU: Cleanup subtarget featuresMatt Arsenault2017-08-071-2/+2
* AMDGPU: Allow SIShrinkInstructions to work in non-SSAMatt Arsenault2017-07-101-3/+3
* [AMDGPU] Switch scalarize global loads ON by defaultAlexander Timofeev2017-07-041-2/+2
* Revert r307026, "[AMDGPU] Switch scalarize global loads ON by default"NAKAMURA Takumi2017-07-041-2/+2
* [AMDGPU] Switch scalarize global loads ON by defaultAlexander Timofeev2017-07-031-2/+2
* [AMDGPU] Resubmit SDWA peephole: enable by defaultSam Kolton2017-04-061-47/+72
* Revert r299536. [AMDGPU] SDWA peephole: enable by default.Ivan Krasin2017-04-051-72/+47
* [AMDGPU] SDWA peephole: enable by defaultSam Kolton2017-04-051-47/+72
* AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernelMatt Arsenault2017-03-211-44/+44
* Enable FeatureFlatForGlobal on Volcanic IslandsMatt Arsenault2017-01-241-1/+1
* [AMDGPU] Do not allow register coalescer to create big superregsStanislav Mekhanoshin2017-01-181-9/+9
* [AMDGPU] Add f16 support (VI+)Konstantin Zhuravlyov2016-11-131-18/+12
* AMDGPU: Add VI i16 supportTom Stellard2016-11-101-11/+25
* Revert "AMDGPU: Add VI i16 support"Tom Stellard2016-11-041-25/+11
* AMDGPU: Add VI i16 supportTom Stellard2016-11-031-11/+25
* AMDGPU: Fix immediate folding logic when shrinking instructionsMatt Arsenault2016-09-091-2/+2
* AMDGPU: Improve load/store of illegal types.Matt Arsenault2016-07-011-62/+23
* AMDGPU: Define priorities for register classesMatt Arsenault2016-05-211-3/+2
* AMDGPU/SI: Enable the post-ra schedulerTom Stellard2016-04-301-2/+2
* AMDGPU/SI: Assembler: Unify parsing/printing of operands.Nikolay Haustov2016-04-291-10/+10
* DAGCombiner: Turn truncate of a bitcasted vector to an extractMatt Arsenault2016-03-011-3/+2
* AMDGPU: Reduce 64-bit lshr by constant to 32-bitMatt Arsenault2016-01-181-2/+0
* AMDGPU: Make v2i64/v2f64 legal types.Matt Arsenault2015-11-251-4/+22
* AMDGPU: Split x8 and x16 vector loads instead of scalarizeMatt Arsenault2015-11-241-24/+66
* Introduce target hook for optimizing register copiesMatt Arsenault2015-09-241-34/+33
* SelectionDAG: Support Expand of f16 extloadsMatt Arsenault2015-09-091-0/+81
* R600 -> AMDGPU renameTom Stellard2015-06-131-0/+525
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