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| author | Tom Stellard <thomas.stellard@amd.com> | 2016-11-10 16:02:37 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2016-11-10 16:02:37 +0000 |
| commit | 115a61560e24e08ecca0b3e2d16e8f1491b47f61 (patch) | |
| tree | a902f8fd2f221164e6ed9be6bbc932083293914a /llvm/test/CodeGen/AMDGPU/half.ll | |
| parent | 2cf393c8fe6ebea1ba041de7e264f2fc7a557ab9 (diff) | |
| download | bcm5719-llvm-115a61560e24e08ecca0b3e2d16e8f1491b47f61.tar.gz bcm5719-llvm-115a61560e24e08ecca0b3e2d16e8f1491b47f61.zip | |
AMDGPU: Add VI i16 support
Patch By: Wei Ding
Differential Revision: https://reviews.llvm.org/D18049
llvm-svn: 286464
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/half.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/half.ll | 36 |
1 files changed, 25 insertions, 11 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/half.ll b/llvm/test/CodeGen/AMDGPU/half.ll index aa1f5b7362d..b63ba8e3632 100644 --- a/llvm/test/CodeGen/AMDGPU/half.ll +++ b/llvm/test/CodeGen/AMDGPU/half.ll @@ -379,19 +379,33 @@ define void @global_extload_v2f16_to_v2f64(<2 x double> addrspace(1)* %out, <2 x ; GCN-LABEL: {{^}}global_extload_v3f16_to_v3f64: -; GCN: buffer_load_dwordx2 [[LOAD:v\[[0-9]+:[0-9]+\]]] -; GCN-DAG: v_cvt_f32_f16_e32 -; GCN-DAG: v_lshrrev_b32_e32 {{v[0-9]+}}, 16, {{v[0-9]+}} -; GCN-DAG: v_cvt_f32_f16_e32 -; GCN-DAG: v_cvt_f32_f16_e32 - -; GCN: v_cvt_f64_f32_e32 -; GCN: v_cvt_f64_f32_e32 -; GCN: v_cvt_f64_f32_e32 +; XSI: buffer_load_dwordx2 [[LOAD:v\[[0-9]+:[0-9]+\]]] +; XSI: v_cvt_f32_f16_e32 +; XSI: v_cvt_f32_f16_e32 +; XSI-DAG: v_lshrrev_b32_e32 {{v[0-9]+}}, 16, {{v[0-9]+}} +; XSI: v_cvt_f32_f16_e32 +; XSI-NOT: v_cvt_f32_f16 + +; XVI: buffer_load_dwordx2 [[LOAD:v\[[0-9]+:[0-9]+\]]] +; XVI: v_cvt_f32_f16_e32 +; XVI: v_cvt_f32_f16_e32 +; XVI-DAG: v_lshrrev_b32_e32 {{v[0-9]+}}, 16, {{v[0-9]+}} +; XVI: v_cvt_f32_f16_e32 +; XVI-NOT: v_cvt_f32_f16 + +; GCN: buffer_load_dwordx2 v{{\[}}[[IN_LO:[0-9]+]]:[[IN_HI:[0-9]+]] +; GCN: v_cvt_f32_f16_e32 [[Z32:v[0-9]+]], v[[IN_HI]] +; GCN: v_cvt_f32_f16_e32 [[X32:v[0-9]+]], v[[IN_LO]] +; GCN: v_lshrrev_b32_e32 [[Y16:v[0-9]+]], 16, v[[IN_LO]] +; GCN: v_cvt_f32_f16_e32 [[Y32:v[0-9]+]], [[Y16]] + +; GCN: v_cvt_f64_f32_e32 [[Z:v\[[0-9]+:[0-9]+\]]], [[Z32]] +; GCN: v_cvt_f64_f32_e32 v{{\[}}[[XLO:[0-9]+]]:{{[0-9]+}}], [[X32]] +; GCN: v_cvt_f64_f32_e32 v[{{[0-9]+}}:[[YHI:[0-9]+]]{{\]}}, [[Y32]] ; GCN-NOT: v_cvt_f64_f32_e32 -; GCN-DAG: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} -; GCN-DAG: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:16 +; GCN-DAG: buffer_store_dwordx4 v{{\[}}[[XLO]]:[[YHI]]{{\]}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} +; GCN-DAG: buffer_store_dwordx2 [[Z]], off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:16 ; GCN: s_endpgm define void @global_extload_v3f16_to_v3f64(<3 x double> addrspace(1)* %out, <3 x half> addrspace(1)* %in) #0 { %val = load <3 x half>, <3 x half> addrspace(1)* %in |
