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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-03-01 21:31:53 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2016-03-01 21:31:53 +0000 |
| commit | b36d462fac8a236b328b00abf053774ff7cd376a (patch) | |
| tree | 993d54a1627f935afd53ce297ed34bcf2c4ab688 /llvm/test/CodeGen/AMDGPU/half.ll | |
| parent | 889e45601e0953393dbe852df06b9d1fa097425a (diff) | |
| download | bcm5719-llvm-b36d462fac8a236b328b00abf053774ff7cd376a.tar.gz bcm5719-llvm-b36d462fac8a236b328b00abf053774ff7cd376a.zip | |
DAGCombiner: Turn truncate of a bitcasted vector to an extract
On AMDGPU where operations i64 operations are often bitcasted to v2i32
and back, this pattern shows up regularly where it breaks some
expected combines on i64, such as load width reducing.
This fixes some test failures in a future commit when i64 loads
are changed to promote.
llvm-svn: 262397
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/half.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/half.ll | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/half.ll b/llvm/test/CodeGen/AMDGPU/half.ll index 76fbc6a5eae..409b2ec8a29 100644 --- a/llvm/test/CodeGen/AMDGPU/half.ll +++ b/llvm/test/CodeGen/AMDGPU/half.ll @@ -396,12 +396,11 @@ define void @global_extload_v2f16_to_v2f64(<2 x double> addrspace(1)* %out, <2 x ; GCN-LABEL: {{^}}global_extload_v3f16_to_v3f64: ; GCN: buffer_load_dwordx2 [[LOAD:v\[[0-9]+:[0-9]+\]]] -; GCN: v_lshrrev_b32_e32 {{v[0-9]+}}, 16, {{v[0-9]+}} - ; GCN: v_cvt_f32_f16_e32 ; GCN: v_cvt_f32_f16_e32 +; GCN-DAG: v_lshrrev_b32_e32 {{v[0-9]+}}, 16, {{v[0-9]+}} ; GCN: v_cvt_f32_f16_e32 -; GCN-NOT: v_cvt_f32_f16_e32 +; GCN-NOT: v_cvt_f32_f16 ; GCN: v_cvt_f64_f32_e32 ; GCN: v_cvt_f64_f32_e32 |
