diff options
| author | Tom Stellard <thomas.stellard@amd.com> | 2016-04-30 00:23:06 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2016-04-30 00:23:06 +0000 |
| commit | cb6ba62d6fce87cc28a5076ccebe05b740d2340d (patch) | |
| tree | a090c0340339618f28dbb530f14c77b5c572588d /llvm/test/CodeGen/AMDGPU/half.ll | |
| parent | 52c68bb0f57fd53e4bd3f721e5fd4ca19544551f (diff) | |
| download | bcm5719-llvm-cb6ba62d6fce87cc28a5076ccebe05b740d2340d.tar.gz bcm5719-llvm-cb6ba62d6fce87cc28a5076ccebe05b740d2340d.zip | |
AMDGPU/SI: Enable the post-ra scheduler
Summary:
This includes a hazard recognizer implementation to replace some of
the hazard handling we had during frame index elimination.
Reviewers: arsenm
Subscribers: qcolombet, arsenm, llvm-commits
Differential Revision: http://reviews.llvm.org/D18602
llvm-svn: 268143
Diffstat (limited to 'llvm/test/CodeGen/AMDGPU/half.ll')
| -rw-r--r-- | llvm/test/CodeGen/AMDGPU/half.ll | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/test/CodeGen/AMDGPU/half.ll b/llvm/test/CodeGen/AMDGPU/half.ll index af409afc496..ba31a70b430 100644 --- a/llvm/test/CodeGen/AMDGPU/half.ll +++ b/llvm/test/CodeGen/AMDGPU/half.ll @@ -396,10 +396,10 @@ define void @global_extload_v2f16_to_v2f64(<2 x double> addrspace(1)* %out, <2 x ; GCN-LABEL: {{^}}global_extload_v3f16_to_v3f64: ; GCN: buffer_load_dwordx2 [[LOAD:v\[[0-9]+:[0-9]+\]]] -; GCN: v_cvt_f32_f16_e32 -; GCN: v_cvt_f32_f16_e32 +; GCN-DAG: v_cvt_f32_f16_e32 ; GCN-DAG: v_lshrrev_b32_e32 {{v[0-9]+}}, 16, {{v[0-9]+}} ; GCN: v_cvt_f32_f16_e32 +; GCN: v_cvt_f32_f16_e32 ; GCN-NOT: v_cvt_f32_f16 ; GCN: v_cvt_f64_f32_e32 |
