summaryrefslogtreecommitdiffstats
path: root/llvm/lib
Commit message (Collapse)AuthorAgeFilesLines
* Revert "blockfreq: Rewrite BlockFrequencyInfoImpl"Duncan P. N. Exon Smith2014-04-184-947/+5
| | | | | | | | | | | This reverts commits r206548, r206549 and r206549. There are some unit tests failing that aren't failing locally [1], so reverting until I have time to investigate. [1]: http://bb.pgr.jp/builders/ninja-x64-msvc-RA-centos6/builds/1816 llvm-svn: 206556
* blockfreq: Really fix r206548 (and r206549)Duncan P. N. Exon Smith2014-04-181-32/+0
| | | | | | Turns out this code is dead. llvm-svn: 206554
* blockfreq: Fixing MSVC after r206548?Duncan P. N. Exon Smith2014-04-181-2/+2
| | | | llvm-svn: 206549
* blockfreq: Rewrite BlockFrequencyInfoImplDuncan P. N. Exon Smith2014-04-184-5/+979
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rewrite the shared implementation of BlockFrequencyInfo and MachineBlockFrequencyInfo entirely. The old implementation had a fundamental flaw: precision losses from nested loops (or very wide branches) compounded past loop exits (and convergence points). The @nested_loops testcase at the end of test/Analysis/BlockFrequencyAnalysis/basic.ll is motivating. This function has three nested loops, with branch weights in the loop headers of 1:4000 (exit:continue). The old analysis gives non-sensical results: Printing analysis 'Block Frequency Analysis' for function 'nested_loops': ---- Block Freqs ---- entry = 1.0 for.cond1.preheader = 1.00103 for.cond4.preheader = 5.5222 for.body6 = 18095.19995 for.inc8 = 4.52264 for.inc11 = 0.00109 for.end13 = 0.0 The new analysis gives correct results: Printing analysis 'Block Frequency Analysis' for function 'nested_loops': block-frequency-info: nested_loops - entry: float = 1.0, int = 8 - for.cond1.preheader: float = 4001.0, int = 32007 - for.cond4.preheader: float = 16008001.0, int = 128064007 - for.body6: float = 64048012001.0, int = 512384096007 - for.inc8: float = 16008001.0, int = 128064007 - for.inc11: float = 4001.0, int = 32007 - for.end13: float = 1.0, int = 8 Most importantly, the frequency leaving each loop matches the frequency entering it. The new algorithm leverages BlockMass and PositiveFloat to maintain precision, separates "probability mass distribution" from "loop scaling", and uses dithering to eliminate probability mass loss. I have unit tests for these types out of tree, but it was decided in the review to make the classes private to BlockFrequencyInfoImpl, and try to shrink them (or remove them entirely) in follow-up commits. The new algorithm should generally have a complexity advantage over the old. The previous algorithm was quadratic in the worst case. The new algorithm is still worst-case quadratic in the presence of irreducible control flow, but it's linear without it. The key difference between the old algorithm and the new is that control flow within a loop is evaluated separately from control flow outside, limiting propagation of precision problems and allowing loop scale to be calculated independently of mass distribution. Loops are visited bottom-up, their loop scales are calculated, and they are replaced by pseudo-nodes. Mass is then distributed through the function, which is now a DAG. Finally, loops are revisited top-down to multiply through the loop scales and the masses distributed to pseudo nodes. There are some remaining flaws. - Irreducible control flow isn't modelled correctly. LoopInfo and MachineLoopInfo ignore irreducible edges, so this algorithm will fail to scale accordingly. There's a note in the class documentation about how to get closer. See also the comments in test/Analysis/BlockFrequencyInfo/irreducible.ll. - Loop scale is limited to 4096 per loop (2^12) to avoid exhausting the 64-bit integer precision used downstream. - The "bias" calculation proposed on llvmdev is *not* incorporated here. This will be added in a follow-up commit, once comments from this review have been handled. llvm-svn: 206548
* R600/SI: Match sign_extend_inreg to s_sext_i32_i8 and s_sext_i32_i16Matt Arsenault2014-04-184-16/+63
| | | | llvm-svn: 206547
* PMBuilder: Expose an option to disable tail callsDuncan P. N. Exon Smith2014-04-181-1/+3
| | | | | | | | Adds API to allow frontends to disable tail calls in PassManagerBuilder. <rdar://problem/16050591> llvm-svn: 206542
* R600/SI: Use SReg_64 instead of VSrc_64 when selecting BUILD_PAIRTom Stellard2014-04-181-1/+1
| | | | llvm-svn: 206541
* [ARM64,C++11] Range'ify another loop.Jim Grosbach2014-04-171-9/+7
| | | | llvm-svn: 206539
* Fix bug 19437 - Only add discriminators for DWARF 4 and above.Diego Novillo2014-04-173-11/+16
| | | | | | | | | | | | | | Summary: This prevents the discriminator generation pass from triggering if the DWARF version being used in the module is prior to 4. Reviewers: echristo, dblaikie CC: llvm-commits Differential Revision: http://reviews.llvm.org/D3413 llvm-svn: 206507
* remove some dead codeNuno Lopes2014-04-176-49/+0
| | | | | | | | | | | | | | | lib/Analysis/IPA/InlineCost.cpp | 18 ------------------ lib/Analysis/RegionPass.cpp | 1 - lib/Analysis/TypeBasedAliasAnalysis.cpp | 1 - lib/Transforms/Scalar/LoopUnswitch.cpp | 21 --------------------- lib/Transforms/Utils/LCSSA.cpp | 2 -- lib/Transforms/Utils/LoopSimplify.cpp | 6 ------ utils/TableGen/AsmWriterEmitter.cpp | 13 ------------- utils/TableGen/DFAPacketizerEmitter.cpp | 7 ------- utils/TableGen/IntrinsicEmitter.cpp | 2 -- 9 files changed, 71 deletions(-) llvm-svn: 206506
* Start pushing changes for Mips Fast-IselReed Kotler2014-04-174-0/+53
| | | | llvm-svn: 206505
* R600: Add comment clariying use of sext for result of MUL_U24Tom Stellard2014-04-171-0/+2
| | | | llvm-svn: 206501
* R600/SI: Stop using i128 as the resource descriptor typeTom Stellard2014-04-176-66/+44
| | | | | | | | | Having i128 as a legal type complicates the legalization phase. v4i32 is already a legal type, so we will use that instead. This fixes several piglit tests. llvm-svn: 206500
* R600/SI: Change default register class for i32 to SReg_32Tom Stellard2014-04-171-1/+1
| | | | | | SIFixSGPRCopies is smart enough to handle this now. llvm-svn: 206499
* R600/SI: Teach SIInstrInfo::moveToVALU() how to handle PHI instructionsTom Stellard2014-04-171-3/+15
| | | | llvm-svn: 206498
* R600/SI: Legalize operands after changing dst reg in FixSGPRCopiesTom Stellard2014-04-171-2/+4
| | | | | | Otherwise we may not legalize some illegal REG_SEQUENCE instructions. llvm-svn: 206497
* Improve ARM64 vector creationLouis Gerbarg2014-04-172-2/+5
| | | | | | | | | | | This patch improves the performance of vector creation in caseiswhere where several of the lanes in the vector are a constant floating point value. It also includes new patterns to fold together some of the instructions when the value is 0.0f. Test cases included. rdar://16349427 llvm-svn: 206496
* ARM64: [su]xtw use W regs as inputs, not X regs.Jim Grosbach2014-04-171-4/+8
| | | | | | | | | Update the SXT[BHW]/UXTW instruction aliases and the shifted reg addressing mode handling. PR19455 and rdar://16650642 llvm-svn: 206495
* ManagedStatic is never built with a null constructor, remove support for it.David Blaikie2014-04-171-2/+3
| | | | llvm-svn: 206492
* ARM64: switch to IR-based atomic operations.Tim Northover2014-04-174-812/+91
| | | | | | | | Goodbye code! (Game: spot the bug fixed by the change). llvm-svn: 206490
* ARM64: add acquire/release versions of the existing atomic intrinsics.Tim Northover2014-04-174-4/+112
| | | | | | | These will be needed to support IR-level lowering of atomic operations. llvm-svn: 206489
* Reverse 206485.Gerolf Hoflehner2014-04-171-8/+2
| | | | | | | | | After some discussions the preferred semantics of the always_inline attribute is inline always when the compiler can determine that it it safe to do so. llvm-svn: 206487
* [stack protector] Make the StackProtector pass respect ssp-buffer-size.Josh Magee2014-04-171-3/+3
| | | | | | | | | | | Previously, SSPBufferSize was assigned the value of the "stack-protector-buffer-size" attribute after all uses of SSPBufferSize. The effect was that the default SSPBufferSize was always used during analysis. I moved the check for the attribute before the analysis; now --param ssp-buffer-size= works correctly again. Differential Revision: http://reviews.llvm.org/D3349 llvm-svn: 206486
* Atomics: promote ARM's IR-based atomics pass to CodeGen.Tim Northover2014-04-178-120/+137
| | | | | | | | | | | | Still only 32-bit ARM using it at this stage, but the promotion allows direct testing via opt and is a reasonably self-contained patch on the way to switching ARM64. At this point, other targets should be able to make use of it without too much difficulty if they want. (See ARM64 commit coming soon for an example). llvm-svn: 206485
* R600/SI: f64 frint is legal on CIMatt Arsenault2014-04-172-2/+4
| | | | llvm-svn: 206475
* [AArch64] Implement the getCSRFirstUseCost API, mirroring that in ARM64.Chad Rosier2014-04-171-0/+7
| | | | llvm-svn: 206473
* Inliner::OptimizationRemark: Fix crash in ↵NAKAMURA Takumi2014-04-171-1/+4
| | | | | | | | clang/test/Frontend/optimization-remark.c on some hosts, including --vg. DebugLoc in Callsite would not live after Inliner. It should be copied before Inliner. llvm-svn: 206459
* [LCG] Just move the allocator (now that we can) when moving a callChandler Carruth2014-04-171-28/+14
| | | | | | | | | graph. This simplifies the custom move constructor operation to one of walking the graph and updating the 'up' pointers to point to the new location of the graph. Switch the nodes from a reference to a pointer for the 'up' edge to facilitate this. llvm-svn: 206450
* [LCG] Remove the Module reference member which we weren't using forChandler Carruth2014-04-171-3/+3
| | | | | | anything and doesn't make sense if assigning. llvm-svn: 206449
* [X86] Add disassembler support for the 0x0f 0x7f form of movq %mm, %mm.Craig Topper2014-04-171-0/+5
| | | | llvm-svn: 206447
* MC: rework static_assert to be MSVC compatibleSaleem Abdulrasool2014-04-171-4/+2
| | | | | | | | Visual Studio does not permit referencing a structure member as a static field for sizeof calculations. Resort to a pointer cast which is compatible across Visual Studio and other compilers. llvm-svn: 206445
* R600/SI: Fix zext from i1 to i64Matt Arsenault2014-04-171-2/+6
| | | | llvm-svn: 206437
* [ARM64] Fix "Cannot select" for vector ctpopAdam Nemet2014-04-171-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit of r205855: Author: Arnold Schwaighofer <aschwaighofer@apple.com> Date: Wed Apr 9 14:20:47 2014 +0000 SLPVectorizer: Only vectorize intrinsics whose operands are widened equally The vectorizer only knows how to vectorize intrinics by widening all operands by the same factor. Patch by Tyler Nowicki! exposed a backend bug causing a regression (Cannot select ctpop). The commit msg is a bit confusing because the patch actually changes the behavior for the loop-vectorizer as well. As things got refactored into a helper ctpop got snuck in to the trivially-vectorizable helper which is now used by both vectorizers. In other words, we started seeing vector-ctpops in the backend. This change makes ctpop LegalizeAction::Expand for the types not supported by the byte-only CNT instruction. We may be able to custom-lower these later to a single CNT but this is to fix the compiler crash first. Fixes <rdar://problem/16578951> llvm-svn: 206433
* Inline a function when the always_inline attributeGerolf Hoflehner2014-04-171-2/+8
| | | | | | | | | | is set even when it contains a indirect branch. The attribute overrules correctness concerns like the escape of a local block address. This is for rdar://16501761 llvm-svn: 206429
* [c++11] Tidy up AsmPrinter.cpp.Jim Grosbach2014-04-161-95/+77
| | | | | | | Range'ify loops and tidy up some by-reference handling. No functional change. llvm-svn: 206422
* Added new functionality to LLVM C API to use DiagnosticInfo to handle errorsTom Stellard2014-04-161-0/+44
| | | | | | Patch by: Darren Powell llvm-svn: 206407
* Replacing a non-ASCII character in a comment with an ASCII character. Fixes ↵Aaron Ballman2014-04-161-1/+1
| | | | | | a C4819 warning in MSVC. llvm-svn: 206403
* Allow diagnostic handlers to check for optimization remarks.Diego Novillo2014-04-161-2/+11
| | | | | | | | | | | | | | | | | | Summary: When optimization remarks are enabled via the driver flag -Rpass, we should allow the FE diagnostic handler to check if the given pass name needs a diagnostic. We were unconditionally checking the pattern defined in opt's -pass-remarks flag. This was causing the FE to not emit any diagnostics. Reviewers: qcolombet CC: llvm-commits Differential Revision: http://reviews.llvm.org/D3362 llvm-svn: 206400
* [mips] Use TwoOperandAliasConstraint for shift instructions.Matheus Almeida2014-04-161-2/+6
| | | | | | | | | | This enables TableGen to generate an additional two operand matcher for our shift_rotate_imm and shift_rotate_reg class of instructions. The tests were also updated so that they include now encoding information for all affected instructions. llvm-svn: 206398
* [mips] Add initial support for NaN2008 in the back-end.Matheus Almeida2014-04-167-11/+78
| | | | | | | | | | | | This is so that EF_MIPS_NAN2008 is set if we are using IEEE 754-2008 NaN encoding (-mnan=2008). This patch also adds support for parsing '.nan legacy' and '.nan 2008' assembly directives. The handling of these directives should match GAS' behaviour i.e., the last directive in use sets the ELF header bit (EF_MIPS_NAN2008). Differential Revision: http://reviews.llvm.org/D3346 llvm-svn: 206396
* ARM64: silence sign-comparison warning.Tim Northover2014-04-161-1/+1
| | | | llvm-svn: 206393
* AArch64/ARM64: produce correct relocation for conditional branches.Tim Northover2014-04-161-1/+5
| | | | llvm-svn: 206391
* [mips] IndentationDaniel Sanders2014-04-161-4/+3
| | | | llvm-svn: 206389
* [mips] Fix emission of '.option pic0' for MIPS-IV.Daniel Sanders2014-04-161-4/+11
| | | | | | | | | | | | Summary: This was a case of incorrect usage of hasMips64() vs isABI_N64() Reviewers: matheusalmeida, dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D3398 llvm-svn: 206388
* [mips] Correct r206370 to account for non-Linux targets using the small data ↵Daniel Sanders2014-04-161-0/+2
| | | | | | | | | | | | section. This should fix the ninja-x64-msvc-RA-centos6 builder. I suspect the check in MipsSubtarget.cpp is incorrect and is really trying to check for a bare-metal target rather and anything other than linux. I'll investigate this. llvm-svn: 206385
* [asan] add two new hidden compile-time flags for asan: ↵Kostya Serebryany2014-04-161-27/+56
| | | | | | asan-instrumentation-with-call-threshold and asan-memory-access-callback-prefix. This is part of the workaround for PR17409 (instrument huge functions with callbacks instead of inlined code). These flags will also help us experiment with kasan (kernel-asan) and clang llvm-svn: 206383
* AArch64/ARM64: port across stub handling for ELF C++ exceptions.Tim Northover2014-04-162-4/+36
| | | | | | | | The most important part here is that we should actuall emit the stubs we refer to in the exception table, but as a side issue this uses more sensible & GCC compatible representations for some of the bits of information. llvm-svn: 206380
* ARM64: use 32-bit moves for constants where possible.Tim Northover2014-04-162-8/+24
| | | | | | | | | | | | If we know that a particular 64-bit constant has all high bits zero, then we can rely on the fact that 32-bit ARM64 instructions automatically zero out the high bits of an x-register. This gives the expansion logic less constraints to satisfy and so sometimes allows it to pick better sequences. Came up while porting test/CodeGen/AArch64/movw-consts.ll: this will allow a 32-bit MOVN to be used in @test8 soon. llvm-svn: 206379
* ARM64: use the integrated assembler on ELF.Tim Northover2014-04-161-0/+2
| | | | llvm-svn: 206378
* [mips] Emit '.set nomicromips' before a function's entry labelMatheus Almeida2014-04-161-3/+2
| | | | | | | | | | | if not in micromips mode. The test (elf_st_other.ll) was renamed as the name and description didn't make sense as the test wasn't checking any symbol table entry. Differential Revision: http://reviews.llvm.org/D3346 llvm-svn: 206377
OpenPOWER on IntegriCloud