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authorMatheus Almeida <matheus.almeida@imgtec.com>2014-04-16 16:28:59 +0000
committerMatheus Almeida <matheus.almeida@imgtec.com>2014-04-16 16:28:59 +0000
commit483d7e9349c15af972e9c06ebf9abec80563ac66 (patch)
treeba63777782545cd8390ea5566d26138391c7ca41 /llvm/lib
parent4bc7731a29b88f78869c1e21b5691618e6363814 (diff)
downloadbcm5719-llvm-483d7e9349c15af972e9c06ebf9abec80563ac66.tar.gz
bcm5719-llvm-483d7e9349c15af972e9c06ebf9abec80563ac66.zip
[mips] Use TwoOperandAliasConstraint for shift instructions.
This enables TableGen to generate an additional two operand matcher for our shift_rotate_imm and shift_rotate_reg class of instructions. The tests were also updated so that they include now encoding information for all affected instructions. llvm-svn: 206398
Diffstat (limited to 'llvm/lib')
-rw-r--r--llvm/lib/Target/Mips/MipsInstrInfo.td8
1 files changed, 6 insertions, 2 deletions
diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.td b/llvm/lib/Target/Mips/MipsInstrInfo.td
index 6e6c0da002c..acc1946a4c2 100644
--- a/llvm/lib/Target/Mips/MipsInstrInfo.td
+++ b/llvm/lib/Target/Mips/MipsInstrInfo.td
@@ -487,14 +487,18 @@ class shift_rotate_imm<string opstr, Operand ImmOpnd,
SDPatternOperator PF = null_frag> :
InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
!strconcat(opstr, "\t$rd, $rt, $shamt"),
- [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr>;
+ [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
+ let TwoOperandAliasConstraint = "$rt = $rd";
+}
class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
SDPatternOperator OpNode = null_frag>:
InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
!strconcat(opstr, "\t$rd, $rt, $rs"),
[(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
- opstr>;
+ opstr> {
+ let TwoOperandAliasConstraint = "$rt = $rd";
+}
// Load Upper Imediate
class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
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