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* IR: Initialize MDNode abbreviations en masse, NFCDuncan P. N. Exon Smith2015-02-041-3/+4
| | | | llvm-svn: 228203
* IR: Define MDNode uniquing sets automatically, NFCDuncan P. N. Exon Smith2015-02-041-3/+2
| | | | llvm-svn: 228200
* Don' try to make sections in comdats SHF_MERGE.Rafael Espindola2015-02-041-4/+4
| | | | | | | | | | | | Parts of llvm were not expecting it and we wouldn't print the entity size of the section. Given what comdats are used for, having SHF_MERGE sections would be just a small improvement, so just disable it for now. Fixes pr22463. llvm-svn: 228196
* R600/SI: Expand misaligned 16-bit memory accessesTom Stellard2015-02-041-0/+5
| | | | llvm-svn: 228190
* R600/SI: Make more store operations legalTom Stellard2015-02-042-12/+0
| | | | | | | | | | | v2i32, i32, trunc i32 to i16, and truc i32 to i8 stores are legal for all address spaces. We had marked them as custom in order to lower them for the private address space, but this is no longer necessary. This enables lowering of misaligned stores of these types in the DAGLegalizer. llvm-svn: 228189
* R600: Don't promote i64 stores to v2i32 during DAG legalizationTom Stellard2015-02-042-3/+25
| | | | | | | We take care of this during instruction selection now. This fixes a potential infinite loop when lowering misaligned stores. llvm-svn: 228188
* StructurizeCFG: Remove obsolete fix for loop backedge detectionTom Stellard2015-02-041-1/+1
| | | | | | | This is no longer needed now that we are using a reverse post-order traversal. llvm-svn: 228187
* StructurizeCFG: Use a reverse post-order traversalTom Stellard2015-02-041-4/+64
| | | | | | | | | | | | | | We were previously doing a post-order traversal and operating on the list in reverse, however this would occasionaly cause backedges for loops to be visited before some of the other blocks in the loop. We know use a reverse post-order traversal, which avoids this issue. The reverse post-order traversal is not completely ideal, so we need to manually fixup the list to ensure that inner loop backedges are visited before outer loop backedges. llvm-svn: 228186
* [Hexagon] Adding selection for GlobalAddress and converting [z/i]ext load ↵Colin LeMahieu2015-02-043-74/+79
| | | | | | patterns to make use of them. llvm-svn: 228184
* Utils: Resolve cycles under distinct MDNodesDuncan P. N. Exon Smith2015-02-041-20/+45
| | | | | | | | Track unresolved nodes under distinct `MDNode`s during `MapMetadata()`, and resolve them at the end. Previously, these cycles wouldn't get resolved. llvm-svn: 228180
* MachineCSE: Clear dead-def flag on CSE.Matthias Braun2015-02-042-2/+17
| | | | | | | | | | | In case CSE reuses a previoulsy unused register the dead-def flag has to be cleared on the def operand, as exposed by the arm64-cse.ll test. This fixes PR22439 and the corresponding rdar://19694987 Differential Revision: http://reviews.llvm.org/D7395 llvm-svn: 228178
* Add range adapters predecessors() and successors() for BBsReid Kleckner2015-02-042-7/+6
| | | | | | | Use them in two isolated transforms so we know they work and aren't dead code. llvm-svn: 228173
* [fuzzer] make multi-process execution more verbose; fix mutation to actually ↵Kostya Serebryany2015-02-046-18/+46
| | | | | | respect mutation depth and to never produce empty units llvm-svn: 228170
* [Hexagon] Replacing some load patterns with cleaner versions.Colin LeMahieu2015-02-041-59/+13
| | | | llvm-svn: 228169
* Fixes a bug in vector load legalization that confused bits and bytes.Michael Kuperstein2015-02-041-3/+3
| | | | | | Differential Revision: http://reviews.llvm.org/D7400 llvm-svn: 228168
* [Hexagon] Adding missing isCodeGenOnly = 0Colin LeMahieu2015-02-041-2/+7
| | | | llvm-svn: 228160
* [Hexagon] Adding encoding information for absolute-reg mode stores. ↵Colin LeMahieu2015-02-042-82/+138
| | | | | | Xfailing a test until constant extenders are correctly put in the same packet. llvm-svn: 228158
* SpecialCaseList: Add support for parsing multiple input files.Alexey Samsonov2015-02-042-39/+56
| | | | | | | | | | | | | | | | | | | | | | | Summary: This change allows users to create SpecialCaseList objects from multiple local files. This is needed to implement a proper support for -fsanitize-blacklist flag (allow users to specify multiple blacklists, in addition to default blacklist, see PR22431). DFSan can also benefit from this change, as DFSan instrumentation pass now accepts ABI-lists both from -fsanitize-blacklist= and -mllvm -dfsan-abilist flags. Go bindings are fixed accordingly. Test Plan: regression test suite Reviewers: pcc Subscribers: llvm-commits, axw, kcc Differential Revision: http://reviews.llvm.org/D7367 llvm-svn: 228155
* [Hexagon] Adding encoding information for absolute-set stores.Colin LeMahieu2015-02-041-12/+34
| | | | llvm-svn: 228154
* [Hexagon] Adding encoding bits for indirect long load instructions.Colin LeMahieu2015-02-041-46/+75
| | | | llvm-svn: 228152
* [ARM] Fix subtarget feature set truncation when using .cpu directiveBradley Smith2015-02-041-2/+1
| | | | | | | This is a bug that was caused due to storing the feature bitset in a 32-bit variable when it is a 64-bit mask, discarding the top half of the feature set. llvm-svn: 228151
* [mips][microMIPS] Implement CodeGen support for SW16 and LW16 instructionsZoran Jovanovic2015-02-046-1/+57
| | | | | | Differential Revision: http://reviews.llvm.org/D6581 llvm-svn: 228149
* [mips] Make MipsSubtarget::hasMips*() functions consistent. NFC.Daniel Sanders2015-02-041-11/+10
| | | | | | | | | | | | Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7377 llvm-svn: 228147
* Fixing a -Wsign-compare warning; NFCAaron Ballman2015-02-041-1/+1
| | | | llvm-svn: 228142
* Adding support to LLVM for targeting Cortex-A72Renato Golin2015-02-042-0/+6
| | | | | | | | | | Currently, Cortex-A72 is modelled as an Cortex-A57 except the fp load balancing pass isn't enabled for Cortex-A72 as it's not profitable to have it enabled for this core. Patch by Ranjeet Singh. llvm-svn: 228140
* [x86] Give movss and movsd execution domains in the x86 backend.Chandler Carruth2015-02-042-16/+23
| | | | | | | | | | | | | This associates movss and movsd with the packed single and packed double execution domains (resp.). While this is largely cosmetic, as we now don't have weird ping-pong-ing between single and double precision, it is also useful because it avoids the domain fixing algorithm from seeing domain breaks that don't actually exist. It will also be much more important if we have an execution domain default other than packed single, as that would cause us to mix movss and movsd with integer vector code on a regular basis, a very bad mixture. llvm-svn: 228135
* Reverting VLD1/VST1 base-updating/post-incrementing combiningRenato Golin2015-02-041-102/+14
| | | | | | | | | | | This reverts patches 223862, 224198, 224203, and 224754, which were all related to the vector load/store combining and were reverted/reaplied a few times due to the same alignment problems we're seeing now. Further tests, mainly self-hosting Clang, will be needed to reapply this patch in the future. llvm-svn: 228129
* [x86] Start to introduce bit-masking based blend lowering.Chandler Carruth2015-02-041-10/+58
| | | | | | | | | | | | This is the simplest form of bit-math based blending which only fires when we are blending with zero and is relatively profitable. I've only enabled this path on very specific lowering strategies. I'm planning to widen its applicability in subsequent patches, but so far you'll notice that even though we get fewer shufps instructions, we *still* do the bit math in the FP execution port. I'm looking into why this is still happening. llvm-svn: 228124
* [x86] Add missing patterns for andps, orps, xorps, and andnps.Chandler Carruth2015-02-041-9/+44
| | | | | | | | | | | | Specifically, the existing patterns were scalar-only. These cover the packed vector bitwise operations when specifically requested with pseudo instructions. This is particularly important in SSE1 where we can't actually emit a logical operation on a v2i64 as that isn't a legal type. This will be tested in subsequent patches which form the floating point and patterns in more places. llvm-svn: 228123
* Replace tabs with spaces from r228116. Oops.Bill Schmidt2015-02-041-2/+2
| | | | llvm-svn: 228117
* [PowerPC] Handle 32-bit targets properly in PPCTLSDynamicCall.cppBill Schmidt2015-02-041-1/+3
| | | | llvm-svn: 228116
* Fix a warning in non-asserts buildsPhilip Reames2015-02-041-0/+1
| | | | llvm-svn: 228114
* Fix some unnoticed/unwanted behavior change from r222319.Frederic Riss2015-02-042-2/+2
| | | | | | | | | The ARM assembler allows register alias redefinitions as long as it targets the same register. r222319 broke that. In the AArch64 case it would just produce a new warning, but in the ARM case it would error out on previously accepted assembler. llvm-svn: 228109
* [fuzzer]: fix exit code, add more diagnosticsKostya Serebryany2015-02-042-1/+2
| | | | llvm-svn: 228103
* [sanitizer] add another workaround for PR 17409: when over a threshold emit ↵Kostya Serebryany2015-02-041-24/+32
| | | | | | coverage instrumentation as calls. llvm-svn: 228102
* Misc documentation/comment fixes.Peter Collingbourne2015-02-042-2/+4
| | | | llvm-svn: 228093
* Clang format of a file introduced in 228090 (NFC)Philip Reames2015-02-041-29/+22
| | | | llvm-svn: 228091
* Add a pass for inserting safepoints into (nearly) arbitrary IRPhilip Reames2015-02-044-0/+996
| | | | | | | | | | | | | | | | | | | | | This pass is responsible for figuring out where to place call safepoints and safepoint polls. It doesn't actually make the relocations explicit; that's the job of the RewriteStatepointsForGC pass (http://reviews.llvm.org/D6975). Note that this code is not yet finalized. Its moving in tree for incremental development, but further cleanup is needed and will happen over the next few days. It is not yet part of the standard pass order. Planned changes in the near future: - I plan on restructuring the statepoint rewrite to use the functions add to the IRBuilder a while back. - In the current pass, the function "gc.safepoint_poll" is treated specially but is not an intrinsic. I plan to make identifying the poll function a property of the GCStrategy at some point in the near future. - As follow on patches, I will be separating a collection of test cases we have out of tree and submitting them upstream. - It's not explicit in the code, but these two patches are introducing a new state for a statepoint which looks a lot like a patchpoint. There's no a transient form which doesn't yet have the relocations explicitly represented, but does prevent reordering of memory operations. Once this is in, I need to update actually make this explicit by reserving the 'unused' argument of the statepoint as a flag, updating the docs, and making the code explicitly check for such a thing. This wasn't really planned, but once I split the two passes - which was done for other reasons - the intermediate state fell out. Just reminds us once again that we need to merge statepoints and patchpoints at some point in the not that distant future. Future directions planned: - Identifying more cases where a backedge safepoint isn't required to ensure timely execution of a safepoint poll. - Tweaking the insertion process to generate easier to optimize IR. (For example, investigating making SplitBackedge) the default. - Adding opt-in flags for a GCStrategy to use this pass. Once done, add this pass to the actual pass ordering. Differential Revision: http://reviews.llvm.org/D6981 llvm-svn: 228090
* Added missing header for the explicit dependency on MDNode.Galina Kistanova2015-02-041-0/+1
| | | | llvm-svn: 228085
* InstrProf: Use a stable sort when reading coverage regionsJustin Bogner2015-02-041-1/+1
| | | | | | | Keeping regions that start at the same location in insertion order makes this logic easier to test / more deterministic. llvm-svn: 228083
* [Hexagon] Revert change to isCodeGenOnly = 1 in r228080Colin LeMahieu2015-02-041-0/+1
| | | | llvm-svn: 228082
* [Hexagon] Changing some isCodeGenOnly to isAsmParserOnly since we want them ↵Colin LeMahieu2015-02-045-40/+39
| | | | | | to asm parse but not cause decode conflicts. llvm-svn: 228080
* Remove a gross usage of environment variables in MachineVerifier, replacing ↵Owen Anderson2015-02-042-96/+77
| | | | | | | | it with support for setting the -verify-machineinstrs flag via an environment variable in LIT. This preserves the handy functionality of force-enabling the MachineVerifier, without the need to embed usage of environment variables in LLVM client applications. llvm-svn: 228079
* InstrProf: Make CounterMappingRegions less confusing to constructJustin Bogner2015-02-031-4/+3
| | | | | | | Creating empty and expansion regions is awkward with the current API. Expose static methods to make this simpler. llvm-svn: 228075
* [PBQP] Provide more information in the debug printsArnaud A. de Grandmaison2015-02-031-1/+74
| | | | | | Based on a patch by Jonas Paulsson llvm-svn: 228068
* Use ImmutableCallSite for statepoint verification.Philip Reames2015-02-031-17/+20
| | | | | | | | | | Patch by: Igor Laevsky "This change generalizes statepoint verification to use ImmutableCallSite instead of CallInst. This will allow to easily implement invoke statepoint verification (in a following change)." Differential Revision: http://reviews.llvm.org/D7308 llvm-svn: 228064
* [LV] Split off memcheck block really at the first checkAdam Nemet2015-02-031-1/+1
| | | | | | | | | | | I've noticed this while trying to move addRuntimeCheck to LoopAccessAnalysis. I think that the intention was to early exit from the overflow checking before the code for the memchecks. This is the entire reason why we compute FirstCheckInst but then we don't use that as the splitting instruction but the final check. Looks like an oversight. llvm-svn: 228056
* [x86] Fix signed vs. unsigned comparison.Chandler Carruth2015-02-031-1/+1
| | | | llvm-svn: 228055
* Fixed unused variable warning.Simon Pilgrim2015-02-031-2/+2
| | | | llvm-svn: 228054
* [Hexagon] Marking a bunch of non-encoded instructions with isCodeGenOnly = 1.Colin LeMahieu2015-02-034-45/+51
| | | | llvm-svn: 228050
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