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| author | Tom Stellard <thomas.stellard@amd.com> | 2015-02-04 20:49:52 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2015-02-04 20:49:52 +0000 |
| commit | 33e64c66ac63d54d496ff8522c141a4256965049 (patch) | |
| tree | b5752db8df4db9a16be8ca964050f3d45f0cae20 /llvm/lib | |
| parent | c7e448c92e71b377df95127cee889b987f58803d (diff) | |
| download | bcm5719-llvm-33e64c66ac63d54d496ff8522c141a4256965049.tar.gz bcm5719-llvm-33e64c66ac63d54d496ff8522c141a4256965049.zip | |
R600/SI: Expand misaligned 16-bit memory accesses
llvm-svn: 228190
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/R600/SIISelLowering.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/R600/SIISelLowering.cpp b/llvm/lib/Target/R600/SIISelLowering.cpp index 4545a5c648c..aeb3d131fb5 100644 --- a/llvm/lib/Target/R600/SIISelLowering.cpp +++ b/llvm/lib/Target/R600/SIISelLowering.cpp @@ -324,6 +324,11 @@ bool SITargetLowering::allowsMisalignedMemoryAccesses(EVT VT, return Align % 4 == 0; } + // Smaller than dword value must be aligned. + // FIXME: This should be allowed on CI+ + if (VT.bitsLT(MVT::i32)) + return false; + // 8.1.6 - For Dword or larger reads or writes, the two LSBs of the // byte-address are ignored, thus forcing Dword alignment. // This applies to private, global, and constant memory. |
