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| author | Renato Golin <renato.golin@linaro.org> | 2015-02-04 13:31:29 +0000 |
|---|---|---|
| committer | Renato Golin <renato.golin@linaro.org> | 2015-02-04 13:31:29 +0000 |
| commit | 60885044993683a47513f583fe965da4b93df0c0 (patch) | |
| tree | 0b0f282a258e6e4b07c1ce4b7ab93003f374d644 /llvm/lib | |
| parent | a5eb775c4d50e9d9a1225a75fb80d3b8a8043cab (diff) | |
| download | bcm5719-llvm-60885044993683a47513f583fe965da4b93df0c0.tar.gz bcm5719-llvm-60885044993683a47513f583fe965da4b93df0c0.zip | |
Adding support to LLVM for targeting Cortex-A72
Currently, Cortex-A72 is modelled as an Cortex-A57 except the fp
load balancing pass isn't enabled for Cortex-A72 as it's not
profitable to have it enabled for this core.
Patch by Ranjeet Singh.
llvm-svn: 228140
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64.td | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM/ARM.td | 4 |
2 files changed, 6 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td index e6a27c386b0..dff48f9ba0d 100644 --- a/llvm/lib/Target/AArch64/AArch64.td +++ b/llvm/lib/Target/AArch64/AArch64.td @@ -91,6 +91,8 @@ def : ProcessorModel<"generic", NoSchedModel, [FeatureFPARMv8, def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>; def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>; +// FIXME: Cortex-A72 is currently modelled as an Cortex-A57. +def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA57]>; def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>; //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td index 244014b5c29..b5641a7bdcb 100644 --- a/llvm/lib/Target/ARM/ARM.td +++ b/llvm/lib/Target/ARM/ARM.td @@ -416,6 +416,10 @@ def : ProcNoItin<"cortex-a53", [ProcA53, HasV8Ops, FeatureAClass, def : ProcNoItin<"cortex-a57", [ProcA57, HasV8Ops, FeatureAClass, FeatureDB, FeatureFPARMv8, FeatureNEON, FeatureDSPThumb2]>; +// FIXME: Cortex-A72 is currently modelled as an Cortex-A57. +def : ProcNoItin<"cortex-a72", [ProcA57, HasV8Ops, FeatureAClass, + FeatureDB, FeatureFPARMv8, + FeatureNEON, FeatureDSPThumb2]>; // Cyclone is very similar to swift def : ProcessorModel<"cyclone", SwiftModel, |
