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* [CodeGen] Avoid handling DBG_VALUE in the LivePhysRegs ↵Matt Davis2018-03-191-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | (addUses,removeDefs,stepForward) Summary: This patch prevents DBG_VALUE instructions from influencing LivePhysRegs::stepBackwards and stepForwards. In at least one case, specifically branch folding, the stepBackwards logic was having an influence on code generation. The result was that certain code compiled with '-g -O2' would differ from that compiled with '-O2' alone. It seems that the original logic, accounting for DBG_VALUE, was influencing the placement of an IMPLICIT_DEF which had a later impact on how blocks were processed in branch folding. Reviewers: kparzysz, MatzeB Reviewed By: kparzysz Subscribers: bjope, llvm-commits Tags: #debug-info Differential Revision: https://reviews.llvm.org/D43850 llvm-svn: 327862
* [demangler] Recopy the demangler from libcxxabi.Erik Pilkington2018-03-191-3943/+4521
| | | | | | | | | Some significant work has gone into libcxxabi's copy of this file: - Uses an AST to represent mangled names. - Support/bugfixes for many C++ features. - Uses LLVM coding style. llvm-svn: 327859
* [InstCombine] canonicalize fcmp+select to fabsSanjay Patel2018-03-191-1/+31
| | | | | | | | | | | | | | This is complicated by -0.0 and nan. This is based on the DAG patterns as shown in D44091. I'm hoping that we can just remove those DAG folds and always rely on IR canonicalization to handle the matching to fabs. We would still need to delete the broken code from DAGCombiner to fix PR36600: https://bugs.llvm.org/show_bug.cgi?id=36600 Differential Revision: https://reviews.llvm.org/D44550 llvm-svn: 327858
* [MachineLICM] Add functions to MachineLICM to hoist invariant storesZaara Syeda2018-03-196-45/+136
| | | | | | | | | | | | | | | | This patch adds functions to allow MachineLICM to hoist invariant stores. Currently, MachineLICM does not hoist any store instructions, however when storing the same value to a constant spot on the stack, the store instruction should be considered invariant and be hoisted. The function isInvariantStore iterates each operand of the store instruction and checks that each register operand satisfies isCallerPreservedPhysReg. The store may be fed by a copy, which is hoisted by isCopyFeedingInvariantStore. This patch also adds the PowerPC changes needed to consider the stack register as caller preserved. Differential Revision: https://reviews.llvm.org/D40196 llvm-svn: 327856
* [X86] Generalize schedule classes to support multiple stagesSimon Pilgrim2018-03-197-567/+308
| | | | | | | | | | | | Currently the WriteResPair style multi-classes take a single pipeline stage and latency, this patch generalizes this to make it easier to create complex schedules with ResourceCycles and NumMicroOps be overriden from their defaults. This has already been done for the Jaguar scheduler to remove a number of custom schedule classes and adding it to the other x86 targets will make it much tidier as we add additional classes in the future to try and replace so many custom cases. I've converted some instructions but a lot of the models need a bit of cleanup after the patch has been committed - memory latencies not being consistent, the class not actually being used when we could remove some/all customs, etc. I'd prefer to keep this as NFC as possible so later patches can be smaller and target specific. Differential Revision: https://reviews.llvm.org/D44612 llvm-svn: 327855
* [x86] put nops into the WriteNop class and customize for JaguarSanjay Patel2018-03-193-5/+7
| | | | | | | | | | | | 1. Given that we already have a classification bucket with 'nop' in the name, that's where 'nop' belongs. Right now, it's only used for prefix bytes and 'pause'. 2. Make the latency of this class '1' for Jaguar to tell the scheduler (and presumably llvm-mca) how to model the resource requirements better even though a nop has no dependencies. Differential Revision: https://reviews.llvm.org/D44608 llvm-svn: 327853
* Changed createTemporaryFile without FD to actually create a file.Ilya Biryukov2018-03-191-7/+32
| | | | | | | | | | | | | | | | | | | | | Summary: This commit changes semantics of createUniqueFile and createTemporaryFile variants that do not return file descriptors. Previously they only checked if files exist, therefore being subject to race conditions. Now they will create an empty file to avoid them. Functions that do not create a file are now called getPotentiallyUniqueTempFileName and getPotentiallyUniqueFileName. Reviewers: klimek, bkramer, krasimir, JDevlieghere, espindola Reviewed By: klimek Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D36827 llvm-svn: 327851
* TableGen: Explicitly forbid self-references to field membersNicolai Haehnle2018-03-192-4/+10
| | | | | | | | | | | | | | | | Summary: Otherwise, patterns like in the test case produce cryptic error messages about fields being resolved incompletely. Change-Id: I713c0191f00fe140ad698675803ab1f8823dc5bd Reviewers: arsenm, craig.topper, tra, MartinO Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D44476 llvm-svn: 327850
* TableGen: Check the dynamic type of !cast<Rec>(string)Nicolai Haehnle2018-03-194-77/+100
| | | | | | | | | | | | | | | | | | | | | Summary: The docs already claim that this happens, but so far it hasn't. As a consequence, existing TableGen files get this wrong a lot, but luckily the fixes are all reasonably straightforward. To make this work with all the existing forms of self-references (since the true type of a record is only built up over time), the lookup of self-references in !cast is delayed until the final resolving step. Change-Id: If5923a72a252ba2fbc81a889d59775df0ef31164 Reviewers: arsenm, craig.topper, tra, MartinO Subscribers: wdng, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D44475 llvm-svn: 327849
* TableGen: Explicitly test some cases of self-references and !cast errorsNicolai Haehnle2018-03-192-7/+7
| | | | | | | | | | | | | | | | | | | | | | | Summary: These are cases of self-references that exist today in practice. Let's add tests for them to avoid regressions. The self-references in PPCInstrInfo.td can be expressed in a simpler way. Allowing this type of self-reference while at the same time consistently doing late-resolve even for self-references is problematic because there are references to fields that aren't in any class. Since there's no need for this type of self-reference anyway, let's just remove it. Change-Id: I914e0b3e1ae7adae33855fac409b536879bc3f62 Reviewers: arsenm, craig.topper, tra, MartinO Subscribers: nemanjai, wdng, kbarton, llvm-commits Differential Revision: https://reviews.llvm.org/D44474 llvm-svn: 327848
* TableGen: Only fold when some operand made resolve progressNicolai Haehnle2018-03-192-5/+19
| | | | | | | | | | | | | | | | Summary: Make sure that we always fold immediately, so there's no point in attempting to re-fold when nothing changes. Change-Id: I069e1989455b6f2ca8606152f6adc1a5e817f1c8 Reviewers: arsenm, craig.topper, tra, MartinO Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D44198 llvm-svn: 327847
* TableGen: Move GenStrConcat to a helper function in BinOpInitNicolai Haehnle2018-03-192-22/+19
| | | | | | | | | | | | | | | Summary: Make it accessible for more users. Change-Id: Ib05f09ba14e7942ced5d2f24b205efa285e40cd5 Reviewers: arsenm, craig.topper, tra, MartinO Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D44196 llvm-svn: 327845
* TableGen: Remove the cast-from-string-to-variable-reference featureNicolai Haehnle2018-03-192-62/+27
| | | | | | | | | | | | | | | | | | | Summary: Cast-from-string for records isn't going away, but cast-from-string for variables is a pretty dodgy feature to have, especially when referencing template arguments. It's doubtful that this ever worked in a reliable way, and nobody seems to be using it, so let's get rid of it and get some related cleanups. Change-Id: I395ac8a43fef4cf98e611f2f552300d21e99b66a Reviewers: arsenm, craig.topper, tra, MartinO Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D44195 llvm-svn: 327844
* AMDGPU/GlobalISel: RegBankSelect for basic int opsMatt Arsenault2018-03-192-0/+4
| | | | llvm-svn: 327843
* AMDGPU: Don't leave dead illegal VGPR->SGPR copiesMatt Arsenault2018-03-191-0/+7
| | | | | | | | | Normally DCE kills these, but at -O0 these get left behind leaving suspicious looking illegal copies. Replace with IMPLICIT_DEF to avoid iterator issues. llvm-svn: 327842
* [MergeICmps] Re-land 324317 "Enable the MergeICmps Pass by default."Clement Courbet2018-03-191-5/+4
| | | | | | Now that PR36557 is fixed. llvm-svn: 327840
* [ARM] Support for v4f16 and v8f16 vectorsSjoerd Meijer2018-03-195-10/+28
| | | | | | | | | | | | This is the groundwork for adding the Armv8.2-A FP16 vector intrinsics, which uses v4f16 and v8f16 vector operands and return values. All the moving parts are tested with two intrinsics, a 1-operand v8f16 and a 2-operand v4f16 intrinsic. In a follow-up patch the rest of the intrinsics and tests will be added. Differential Revision: https://reviews.llvm.org/D44538 llvm-svn: 327839
* Stylish change. NFCXin Tong2018-03-191-2/+2
| | | | llvm-svn: 327838
* [SystemZ] Bugfix of CC liveness in emitMemMemWrapper (CLC).Jonas Paulsson2018-03-191-0/+4
| | | | | | | | | If DoneMBB becomes empty it must have CC added to its live-in list, since it will fall-through into EndMBB. This happens when the CLC loop does the complete range. Review: Ulrich Weigand llvm-svn: 327834
* HexagonISelLowering.cpp: fix 'enum in bool context' warningHans Wennborg2018-03-191-2/+2
| | | | llvm-svn: 327832
* [RISCV] Peephole optimisation for load/store of global values or constant ↵Alex Bradbury2018-03-191-0/+95
| | | | | | | | | | | addresses (load (add base, off), 0) -> (load base, off) (store val, (add base, off)) -> (store val, base, off) This is similar to an equivalent peephole optimisation in PPCISelDAGToDAG. llvm-svn: 327831
* [MSan] fix the types of RegSaveAreaPtrPtr and OverflowArgAreaPtrPtrAlexander Potapenko2018-03-191-6/+6
| | | | | | | | | | | | | | Despite their names, RegSaveAreaPtrPtr and OverflowArgAreaPtrPtr used to be i8* instead of i8**. This is important, because these pointers are dereferenced twice (first in CreateLoad(), then in getShadowOriginPtr()), but for some reason MSan allowed this - most certainly because it was possible to optimize getShadowOriginPtr() away at compile time. Differential revision: https://reviews.llvm.org/D44520 llvm-svn: 327830
* [MSan] Don't create zero offsets in getShadowPtrForArgument(). NFCAlexander Potapenko2018-03-191-2/+4
| | | | | | | | | | | | | | For MSan instrumentation with MS.ParamTLS and MS.ParamOriginTLS being TLS variables, the CreateAdd() with ArgOffset==0 is a no-op, because the compiler is able to fold the addition of 0. But for KMSAN, which receives ParamTLS and ParamOriginTLS from a call to the runtime library, this introduces a stray instruction which complicates reading/testing the IR. Differential revision: https://reviews.llvm.org/D44514 llvm-svn: 327829
* [MSan] Introduce insertWarningFn(). NFCAlexander Potapenko2018-03-191-15/+16
| | | | | | | | | | | This is a step towards the upcoming KMSAN implementation patch. KMSAN is going to use a different warning function, __msan_warning_32(uptr origin), so we'd better create the warning calls in one place. Differential Revision: https://reviews.llvm.org/D44513 llvm-svn: 327828
* [ARM] Fix warnings about missing parentheses in ARMAsmParserMikhail Maltsev2018-03-191-3/+6
| | | | llvm-svn: 327827
* [SCEV] Factor out isKnownViaInduction. NFC.Serguei Katkov2018-03-191-49/+38
| | | | | | | | | | | This just extracts the isKnownViaInduction from isKnownPredicate. Reviewers: sanjoy, mkazantsev, reames Reviewed By: mkazantsev Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D44554 llvm-svn: 327824
* [SCEV] Re-land: Fix isKnownPredicateSerguei Katkov2018-03-191-27/+73
| | | | | | | | | | | | | | | | | This is re-land of https://reviews.llvm.org/rL327362 with a fix and regression test. The crash was due to it is possible that for found MDL loop, LHS or RHS may contain an invariant unknown SCEV which does not dominate the MDL. Please see regression test for an example. Reviewers: sanjoy, mkazantsev, reames Reviewed By: mkazantsev Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D44553 llvm-svn: 327822
* [X86] Merge XADD8rr regular expression with XADD16rr/XADD32rr/XADD64rr in a ↵Craig Topper2018-03-192-4/+2
| | | | | | couple scheduler models. llvm-svn: 327821
* [X86] Add ADD16i16/ADD32i32/ADD64i32 and similar to the scheduler models to ↵Craig Topper2018-03-195-34/+40
| | | | | | | | match ADD8i8. Also move ADC8i8 and SBB8i8 in the Sandy Bridge model to the same class as ADC8ri and SBB8ri. That seems more accurate since its the 8i8 is just the register forced to AL instead of coming from modrm. llvm-svn: 327820
* [X6] Remove two unused InstrItinClassCraig Topper2018-03-192-4/+0
| | | | llvm-svn: 327819
* [X86] Use IIC_CMOV64_RR/RM on 64-bit cmov instructions.Craig Topper2018-03-191-2/+2
| | | | llvm-svn: 327817
* [X86] Merge 32 and 64-bit RORX/SHLX/SARX/SHRX into single regular ↵Craig Topper2018-03-192-16/+8
| | | | | | expressions in scheduler models. llvm-svn: 327816
* [X86] Merge 8-bit instructions into instregex with 16/32/64 instructions in ↵Craig Topper2018-03-195-945/+473
| | | | | | | | the scheduler models as much as possible. NFCI This reduces the total number of generated scheduler classes from 5404 to 5316. llvm-svn: 327815
* [AVR] Lower i128 divisions to runtime library callsDylan McKay2018-03-191-0/+3
| | | | | | | | | | | This patch adds i128 division support by instruction LLVM to lower 128-bit divisions to the __udivmodti4 and __divmodti4 rtlib functions. This also adds test for 64-bit division and 128-bit division. Patch by Peter Nimmervoll. llvm-svn: 327814
* [Mips] Remove duplicate lines from MipsScheduleP5600.td and enable ↵Craig Topper2018-03-181-21/+0
| | | | | | | | FullInstRWOverlapCheck. This fixes the errors found by the new check added in r327808. llvm-svn: 327813
* [AArch64] Fix a few InstRWs in the A53 scheduler model and enable ↵Craig Topper2018-03-181-7/+4
| | | | | | | | FullInstRWOverlapCheck. This fixes the errors found by the new check added in r327808. llvm-svn: 327812
* [TableGen] When trying to reuse a scheduler class for instructions from an ↵Craig Topper2018-03-1816-0/+47
| | | | | | | | | | | | InstRW, make sure we haven't already seen another InstRW containing this instruction on this CPU. This is similar to the check later when we remap some of the instructions from one class to a new one. But if we reuse the class we don't get to do that check. So many CPUs have violations of this check that I had to add a flag to the SchedMachineModel to allow it to be disabled. Hopefully we can get those cleaned up quickly and remove this flag. A lot of the violations are due to overlapping regular expressions, but that's not the only kind of issue it found. llvm-svn: 327808
* [X86][Btver2] Fix crc32 schedule costsSimon Pilgrim2018-03-181-0/+16
| | | | | | The default is currently FAdd for some reason llvm-svn: 327807
* [X86][Btver2] FADD/FHADD ymm instructions are double pumped on the JFPA ↵Simon Pilgrim2018-03-181-8/+8
| | | | | | functional pipe llvm-svn: 327804
* [X86][Btver2] Float bitwise ymm instructions are double pumped on the JFPX ↵Simon Pilgrim2018-03-181-4/+4
| | | | | | (JFPA/JFPM) functional pipes llvm-svn: 327803
* [X86][Btver2] F16C instructions are performed on the JSTC functional pipeSimon Pilgrim2018-03-181-11/+11
| | | | llvm-svn: 327801
* [LICM] Salvage DI from dying InstructionsAnastasis Grammenos2018-03-181-0/+1
| | | | | | | LICM deletes trivially dead instructions which it won't attempt to sink. Attempt to salvage debug values which reference these instructions. llvm-svn: 327800
* [InstCombine] peek through unsigned FP casts for zero-equality compares ↵Roman Lebedev2018-03-181-0/+9
| | | | | | | | | | | | | | | | | | | | | | (PR36682) Summary: This pattern came up in PR36682 / D44390 https://bugs.llvm.org/show_bug.cgi?id=36682 https://reviews.llvm.org/D44390 https://godbolt.org/g/oKvT5H See also D44416 Reviewers: spatel, majnemer, efriedma, arsenm Reviewed By: spatel Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D44424 llvm-svn: 327799
* [InstCombine] add nnan requirement for sqrt(x) * sqrt(y) -> sqrt(x*y)Sanjay Patel2018-03-181-1/+3
| | | | | | This is similar to D43765. llvm-svn: 327797
* [InstSimplify] loosen FMF for sqrt(X) * sqrt(X) --> XSanjay Patel2018-03-181-3/+6
| | | | | | | | | As shown in the code comment, we don't need all of 'fast', but we do need reassoc + nsz + nnan. Differential Revision: https://reviews.llvm.org/D43765 llvm-svn: 327796
* [X86][Btver2] Strip default latency/resource values. NFCI.Simon Pilgrim2018-03-181-10/+7
| | | | llvm-svn: 327795
* [X86][Btver2] SSE4A EXTRQ/INSERTQ instructions are performed on the ↵Simon Pilgrim2018-03-181-5/+3
| | | | | | JVALU0/JVALU1 functional pipes llvm-svn: 327794
* [X86][Btver2] Modelled float bitwise instructions as being performed on the ↵Simon Pilgrim2018-03-181-11/+25
| | | | | | float cluster (FPA/FPM) not the integer. llvm-svn: 327793
* [X86][Btver2] Correctly distinguish between scheduling pipe and functional ↵Simon Pilgrim2018-03-181-26/+31
| | | | | | | | | | unit for JWriteResFpuPair defs Jaguar's FPU has 2 scheduler pipes (JFPU0/JFPU1) which forward to multiple functional sub-units each. We need to model that an micro-op will both consume the scheduler pipe and a functional unit. This patch just handles the ops defined through JWriteResFpuPair, I'll go through the custom cases later. llvm-svn: 327791
* [dsymutil] Rename llvm-dsymutil -> dsymutilJonas Devlieghere2018-03-181-1/+1
| | | | | | | | | | | Now that almost all functionality of Apple's dsymutil has been upstreamed, the open source variant can be used as a drop in replacement. Hence we feel it's no longer necessary to have the llvm prefix. Differential revision: https://reviews.llvm.org/D44527 llvm-svn: 327790
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