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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-03-18 15:59:51 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-03-18 15:59:51 +0000 |
| commit | 87d2f7463fe985d2b3769afee3a725f180f148ba (patch) | |
| tree | 1e57774592af1b238e4da0de3467c1ca3c5ef0ce /llvm/lib | |
| parent | 3a589103a4aa532d62c2c579e78e766e46f752c8 (diff) | |
| download | bcm5719-llvm-87d2f7463fe985d2b3769afee3a725f180f148ba.tar.gz bcm5719-llvm-87d2f7463fe985d2b3769afee3a725f180f148ba.zip | |
[X86][Btver2] F16C instructions are performed on the JSTC functional pipe
llvm-svn: 327801
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86ScheduleBtVer2.td | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/llvm/lib/Target/X86/X86ScheduleBtVer2.td b/llvm/lib/Target/X86/X86ScheduleBtVer2.td index b5310cdf683..b59d258155e 100644 --- a/llvm/lib/Target/X86/X86ScheduleBtVer2.td +++ b/llvm/lib/Target/X86/X86ScheduleBtVer2.td @@ -416,45 +416,45 @@ def : InstRW<[JWriteINSERTQ], (instrs INSERTQ, INSERTQI)>; // F16C instructions. //////////////////////////////////////////////////////////////////////////////// -def JWriteCVT3: SchedWriteRes<[JFPU1]> { +def JWriteCVT3: SchedWriteRes<[JFPU1, JSTC]> { let Latency = 3; } def : InstRW<[JWriteCVT3], (instrs VCVTPS2PHrr, VCVTPH2PSrr)>; -def JWriteCVT3St: SchedWriteRes<[JFPU1, JSAGU]> { +def JWriteCVT3St: SchedWriteRes<[JFPU1, JSTC, JSAGU]> { let Latency = 3; } def : InstRW<[JWriteCVT3St], (instrs VCVTPS2PHmr)>; -def JWriteCVT3Ld: SchedWriteRes<[JLAGU, JFPU1]> { +def JWriteCVT3Ld: SchedWriteRes<[JLAGU, JFPU1, JSTC]> { let Latency = 8; } def : InstRW<[JWriteCVT3Ld], (instrs VCVTPH2PSrm)>; -def JWriteCVTPS2PHY: SchedWriteRes<[JFPU1, JFPU01]> { +def JWriteCVTPS2PHY: SchedWriteRes<[JFPU1, JSTC, JFPX]> { let Latency = 6; - let ResourceCycles = [2, 2]; + let ResourceCycles = [2, 2, 2]; let NumMicroOps = 3; } def : InstRW<[JWriteCVTPS2PHY], (instrs VCVTPS2PHYrr)>; -def JWriteCVTPS2PHYSt: SchedWriteRes<[JFPU1, JFPU01, JSAGU]> { +def JWriteCVTPS2PHYSt: SchedWriteRes<[JFPU1, JSTC, JFPX, JSAGU]> { let Latency = 11; - let ResourceCycles = [2, 2, 1]; + let ResourceCycles = [2, 2, 2, 1]; let NumMicroOps = 3; } def : InstRW<[JWriteCVTPS2PHYSt], (instrs VCVTPS2PHYmr)>; -def JWriteCVTPH2PSY: SchedWriteRes<[JFPU1]> { +def JWriteCVTPH2PSY: SchedWriteRes<[JFPU1, JSTC]> { let Latency = 3; - let ResourceCycles = [2]; + let ResourceCycles = [2, 2]; let NumMicroOps = 2; } def : InstRW<[JWriteCVTPH2PSY], (instrs VCVTPH2PSYrr)>; -def JWriteCVTPH2PSYLd: SchedWriteRes<[JLAGU, JFPU1]> { +def JWriteCVTPH2PSYLd: SchedWriteRes<[JLAGU, JFPU1, JSTC]> { let Latency = 8; - let ResourceCycles = [1, 2]; + let ResourceCycles = [1, 2, 2]; let NumMicroOps = 2; } def : InstRW<[JWriteCVTPH2PSYLd], (instrs VCVTPH2PSYrm)>; |

