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| author | Craig Topper <craig.topper@intel.com> | 2018-03-19 04:21:42 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@intel.com> | 2018-03-19 04:21:42 +0000 |
| commit | e18fbab988e3f64424fddafdfbe9672cba710a69 (patch) | |
| tree | 7fb003d785fc6af59144476287e8b52c3770987d /llvm/lib | |
| parent | d10ceffa5f33f50513516030c9f265cc4d6b168a (diff) | |
| download | bcm5719-llvm-e18fbab988e3f64424fddafdfbe9672cba710a69.tar.gz bcm5719-llvm-e18fbab988e3f64424fddafdfbe9672cba710a69.zip | |
[X86] Merge XADD8rr regular expression with XADD16rr/XADD32rr/XADD64rr in a couple scheduler models.
llvm-svn: 327821
Diffstat (limited to 'llvm/lib')
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedSandyBridge.td | 3 | ||||
| -rwxr-xr-x | llvm/lib/Target/X86/X86SchedSkylakeServer.td | 3 |
2 files changed, 2 insertions, 4 deletions
diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td index f934e4abfeb..b7613f4fcbf 100644 --- a/llvm/lib/Target/X86/X86SchedSandyBridge.td +++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td @@ -1055,8 +1055,7 @@ def SBWriteResGroup25 : SchedWriteRes<[SBPort015]> { def: InstRW<[SBWriteResGroup25], (instregex "LEAVE64")>; def: InstRW<[SBWriteResGroup25], (instregex "OUT32rr")>; def: InstRW<[SBWriteResGroup25], (instregex "OUT8rr")>; -def: InstRW<[SBWriteResGroup25], (instregex "XADD(16|32|64)rr")>; -def: InstRW<[SBWriteResGroup25], (instregex "XADD8rr")>; +def: InstRW<[SBWriteResGroup25], (instregex "XADD(8|16|32|64)rr")>; def SBWriteResGroup25_2 : SchedWriteRes<[SBPort5,SBPort05]> { let Latency = 3; diff --git a/llvm/lib/Target/X86/X86SchedSkylakeServer.td b/llvm/lib/Target/X86/X86SchedSkylakeServer.td index 16a10989c6a..130d0d628e2 100755 --- a/llvm/lib/Target/X86/X86SchedSkylakeServer.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeServer.td @@ -2105,8 +2105,7 @@ def SKXWriteResGroup36 : SchedWriteRes<[SKXPort0156]> { let NumMicroOps = 3; let ResourceCycles = [3]; } -def: InstRW<[SKXWriteResGroup36], (instregex "XADD(16|32|64)rr")>; -def: InstRW<[SKXWriteResGroup36], (instregex "XADD8rr")>; +def: InstRW<[SKXWriteResGroup36], (instregex "XADD(8|16|32|64)rr")>; def: InstRW<[SKXWriteResGroup36], (instregex "XCHG8rr")>; def SKXWriteResGroup37 : SchedWriteRes<[SKXPort0,SKXPort5]> { |
