diff options
author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2020-01-15 12:36:11 +0000 |
---|---|---|
committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2020-01-15 12:37:37 +0000 |
commit | e26a78e70857273c83aaacd4aa0edb36effe70e3 (patch) | |
tree | 2fe706f04e194cf4017f101849a60da46a1810f9 /llvm/lib/Target | |
parent | 7bc58a779aaa1de56fad8b1bc8e46932d2f2f1e4 (diff) | |
download | bcm5719-llvm-e26a78e70857273c83aaacd4aa0edb36effe70e3.tar.gz bcm5719-llvm-e26a78e70857273c83aaacd4aa0edb36effe70e3.zip |
Revert rG6078f2fedcac5797ac39ee5ef3fd7a35ef1202d5 - "[AArch64][GlobalISel]: Support @llvm.{return,frame}address selection."
These intrinsics expand to a variable number of instructions so just like in
ISelLowering.cpp we use custom code to deal with them.
Committing Tim's original patch.
Differential Revision: https://reviews.llvm.org/D65656
----
Breaks EXPENSIVE_CHECKS builds.
Diffstat (limited to 'llvm/lib/Target')
-rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp | 39 |
1 files changed, 1 insertions, 38 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp index 9f9cc7d7c9e..b9ac2657e1c 100644 --- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -4091,7 +4091,7 @@ bool AArch64InstructionSelector::selectIntrinsic( switch (IntrinID) { default: break; - case Intrinsic::aarch64_crypto_sha1h: { + case Intrinsic::aarch64_crypto_sha1h: Register DstReg = I.getOperand(0).getReg(); Register SrcReg = I.getOperand(2).getReg(); @@ -4130,43 +4130,6 @@ bool AArch64InstructionSelector::selectIntrinsic( I.eraseFromParent(); return true; } - case Intrinsic::frameaddress: - case Intrinsic::returnaddress: { - MachineFunction &MF = *I.getParent()->getParent(); - MachineFrameInfo &MFI = MF.getFrameInfo(); - - unsigned Depth = I.getOperand(2).getImm(); - Register DstReg = I.getOperand(0).getReg(); - RBI.constrainGenericRegister(DstReg, AArch64::GPR64RegClass, MRI); - - if (Depth == 0 && IntrinID == Intrinsic::returnaddress) { - MFI.setReturnAddressIsTaken(true); - MF.addLiveIn(AArch64::LR, &AArch64::GPR64RegClass); - I.getParent()->addLiveIn(AArch64::LR); - MIRBuilder.buildCopy({DstReg}, {Register(AArch64::LR)}); - I.eraseFromParent(); - return true; - } - - MFI.setFrameAddressIsTaken(true); - Register FrameAddr(AArch64::FP); - while (Depth--) { - Register NextFrame = MRI.createVirtualRegister(&AArch64::GPR64RegClass); - MIRBuilder.buildInstr(AArch64::LDRXui, {NextFrame}, {FrameAddr}).addImm(0); - FrameAddr = NextFrame; - } - - if (IntrinID == Intrinsic::frameaddress) - MIRBuilder.buildCopy({DstReg}, {FrameAddr}); - else { - MFI.setReturnAddressIsTaken(true); - MIRBuilder.buildInstr(AArch64::LDRXui, {DstReg}, {FrameAddr}).addImm(1); - } - - I.eraseFromParent(); - return true; - } - } return false; } |