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* [X86] Directly emit a BROADCAST_LOAD from constant pool in lowerUINT_TO_FP_vX...Craig Topper2020-01-141-2/+12
* [AIX][XCOFF] Supporting the ReadOnlyWithRel SectionKnddiggerlin2020-01-141-2/+1
* [ARM][MVE] VTP Block Pass fixSjoerd Meijer2020-01-141-2/+2
* [AArch64] Fix save register pairing for Windows AAPCSSanne Wouda2020-01-141-4/+16
* [AIX] ExternalSymbolSDNode loweringXiangling Liao2020-01-141-24/+64
* Make helper functions static or move them into anonymous namespaces. NFC.Benjamin Kramer2020-01-142-4/+4
* [ARM,MVE] Use the new Tablegen `defvar` and `if` statements.Simon Tatham2020-01-141-253/+232
* [ARM][LowOverheadLoops] Allow all MVE instrs.Sam Parker2020-01-141-21/+18
* [ARM][LowOverheadLoops] Change predicate inspectionSam Parker2020-01-141-26/+27
* [ARM][Thumb2] Fix ADD/SUB invalid writes to SPDiogo Sampaio2020-01-147-86/+351
* [ARM][MVE] Disallow VPSEL for tail predicationSam Parker2020-01-142-4/+16
* [ARM][MVE] Masked gathers from base + vector of offsetsAnna Welker2020-01-141-38/+162
* [AMDGPU] Model distance to instruction in bundleStanislav Mekhanoshin2020-01-141-5/+17
* [AMDGPU] Fix getInstrLatency() always returning 1Stanislav Mekhanoshin2020-01-142-3/+7
* [X86] Copy the nofpexcept flag when folding a load into an instruction using ...Craig Topper2020-01-131-0/+4
* [GlobalISel] Change representation of shuffle masks in MachineOperand.Eli Friedman2020-01-131-6/+3
* [X86][Disassembler] Fix a bug when disassembling an empty stringFangrui Song2020-01-131-1/+3
* AMDGPU/GlobalISel: Select llvm.amdgcn.ds.ordered.{add|swap}Matt Arsenault2020-01-132-0/+88
* AMDGPU/GlobalISel: Set insert point after waterfall loopMatt Arsenault2020-01-131-2/+3
* AMDGPU/GlobalISel: Fix branch targets when emitting SI_IFMatt Arsenault2020-01-131-7/+30
* AMDGPU/GlobalISel: Simplify assertMatt Arsenault2020-01-131-11/+3
* [Scheduler] Remove superfluous casts. NFCDavid Green2020-01-131-1/+1
* [AArch64][SVE] Add patterns for some arith SVE instructions.Danilo Carvalho Grael2020-01-135-10/+67
* [RISCV] Handle globals and block addresses in asm operandsLuís Marques2020-01-131-0/+8
* [AArch64] Emit HINT instead of PAC insns in Armv8.2-A or belowPablo Barrio2020-01-131-15/+33
* [MIPS] Don't emit R_(MICRO)MIPS_JALR relocations against data symbolsAlex Richardson2020-01-131-0/+9
* [X86] Fix MSVC "truncation from 'int' to 'bool'" warning. NFCI.Simon Pilgrim2020-01-131-2/+2
* ARMLowOverheadLoops: return earlier to avoid printing irrelevant dbg msg. NFCSjoerd Meijer2020-01-131-0/+1
* This option allows selecting the TLS size in the local exec TLS model,KAWASHIMA Takahiro2020-01-133-26/+117
* [RISCV] Collect Statistics on Compressed InstructionsSam Elliott2020-01-132-0/+14
* [X86] Use SDNPOptInGlue instead of SDNPInGlue on a couple SDNodes.Craig Topper2020-01-121-2/+2
* AMDGPU/GlobalISel: Don't use XEXEC class for SGPRsMatt Arsenault2020-01-121-1/+1
* AMDGPU/GlobalISel: Copy type when inserting readfirstlaneMatt Arsenault2020-01-121-0/+2
* [RISCV] Check register class for AMO memory operandsJames Clarke2020-01-132-1/+6
* [PowerPC] Delete PPCDarwinAsmPrinter and PPCMCAsmInfoDarwinFangrui Song2020-01-124-201/+1
* [X86][AVX] Use lowerShuffleAsLanePermuteAndSHUFP to lower binary v4f64 shuffles.Simon Pilgrim2020-01-121-0/+12
* [X86][AVX] lowerShuffleAsLanePermuteAndSHUFP - only set the demanded elements...Simon Pilgrim2020-01-121-2/+1
* [X86][Disassembler] Merge X86DisassemblerDecoder.cpp into X86Disassembler.cpp...Fangrui Song2020-01-124-1868/+1569
* [X86][Disassembler] SimplifyFangrui Song2020-01-123-45/+7
* [X86] Don't call LowerSETCC from LowerSELECT for STRICT_FSETCC/STRICT_FSETCCS...Craig Topper2020-01-111-3/+1
* [TargetLowering][X86] Connect the chain from STRICT_FSETCC in TargetLowering:...Craig Topper2020-01-111-2/+4
* [X86][Disassembler] Optimize argument passing and immediate readingFangrui Song2020-01-113-74/+41
* [Disassembler] Delete the VStream parameter of MCDisassembler::getInstruction()Fangrui Song2020-01-1120-69/+32
* [X86][Disassembler] Replace custom logger with LLVM_DEBUGFangrui Song2020-01-113-56/+14
* [X86][Disassembler] Simplify and optimize reader functionsFangrui Song2020-01-113-180/+101
* [X86] Turn FP_ROUND/STRICT_FP_ROUND into X86ISD::VFPROUND/STRICT_VFPROUND dur...Craig Topper2020-01-113-67/+4
* [X86] Adjust nop emission by compiler to consider target decode limitationsPhilip Reames2020-01-111-0/+17
* [X86AsmBackend] Move static function before sole use [NFC]Philip Reames2020-01-111-34/+34
* [X86AsmBackend] Be consistent about placing definitions out of line [NFC]Philip Reames2020-01-111-49/+57
* [X86] Fix outdated commentSimon Pilgrim2020-01-111-2/+1
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