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* [X86] Add custom lowering for v2i64->v2f32 strict_sint_to_fp/strict_uint_to_f...Craig Topper2019-12-261-8/+32
* [PowerPC] stop folding if result rlwinm mask is wrap while original rlwinm is...czhengsz2019-12-251-2/+6
* [NFC][PowerPC] Add a function tryAndWithMask to handle all the casesQingShan Zhang2019-12-261-111/+120
* [PowerPC] Modify the hasSideEffects of MTLR and MFLR from 1 to 0Kang Zhang2019-12-262-0/+4
* [X86] Enable STRICT_SINT_TO_FP/STRICT_UINT_TO_FP on X86 backendWang, Pengfei2019-12-265-46/+141
* [X86] Use zero vector to extend to 512-bits for strict_fp_to_uint v2i1->v2f64...Craig Topper2019-12-251-3/+7
* [X86FixupSetCC] Remember the preceding eflags defining instruction while we'r...Craig Topper2019-12-251-27/+5
* [X86] Merge together some common code in LowerFP_TO_INT now that we have STRI...Craig Topper2019-12-251-17/+11
* Add missing strict_fp_to_intLiu, Chen32019-12-251-0/+3
* [X86FixupSetCC] Use MachineInstr::readRegister/definesRegister to check for E...Craig Topper2019-12-241-15/+3
* [WinEH] Delete addFnAttr("no-frame-pointer-elim") which seems no longer neededFangrui Song2019-12-241-5/+0
* AMDGPU/GlobalISel: Fix mapping and selection of llvm.amdgcn.div.fixupMatt Arsenault2019-12-242-1/+6
* [X86] Use 128-bit vector instructions for f32/f64->i64 conversions on 32-bit ...Craig Topper2019-12-241-7/+14
* [X86] Add STRICT versions of CVTTP2SI, CVTTP2UI, CMPM, and CMPP.Craig Topper2019-12-246-165/+182
* AMDGPU/GlobalISel: Legalize some 16-bit round instructionsMatt Arsenault2019-12-241-1/+6
* AMDGPU/GlobalISel: Lower llvm.amdgcn.elseMatt Arsenault2019-12-241-6/+17
* [SelectionDAG] Change SelectionDAGISel::{funcInfo,SDB} to use unique_ptrFangrui Song2019-12-231-8/+9
* [FPEnv][X86] More strict int <-> FP conversion fixesUlrich Weigand2019-12-234-92/+90
* [AMDGPU] Don't create MachinePointerInfos with an UndefValue pointerJay Foad2019-12-235-34/+11
* [DAGCombine] visitEXTRACT_SUBVECTOR - 'little to big' extract_subvector(bitca...Sanjay Patel2019-12-232-97/+0
* [AArch64] [Windows] Use COFF stubs for calls to extern_weak functionsMartin Storsjö2019-12-233-7/+15
* [ARM] [Windows] Use COFF stubs for calls to extern_weak functionsMartin Storsjö2019-12-231-4/+6
* [NFC] Style cleanupsShengchen Kan2019-12-231-22/+23
* [Power9] Remove the PPCISD::XXREVERSE as it has completely the same semantics...QingShan Zhang2019-12-234-23/+5
* [AVR] Fix codegen for rotate instructionsJim Lin2019-12-233-4/+104
* [PowerPC] Exploit `vrl(b|h|w|d)` to perform vector rotationKai Luo2019-12-232-1/+21
* [AMDGPU] Fixes -Wrange-loop-analysis warningsMark de Wever2019-12-222-4/+4
* [Hexagon] Fixes -Wrange-loop-analysis warningsMark de Wever2019-12-225-10/+10
* [NVPTX] Fixes -Wrange-loop-analysis warningsMark de Wever2019-12-221-1/+1
* [PowerPC] Fixes -Wrange-loop-analysis warningsMark de Wever2019-12-221-3/+3
* [ms] [X86] Use "P" modifier on operands to call instructions in inline X86 as...Eric Astor2019-12-224-13/+41
* [AArch64] match splat of bitcasted extract subvector to DUPLANESanjay Patel2019-12-221-7/+43
* Fix "result of 32-bit shift implicitly converted to 64 bits" warning. NFC.Simon Pilgrim2019-12-211-1/+1
* [AArch64] Respect reserved registers while renaming in LdSt opt.Florian Hahn2019-12-211-1/+4
* AMDGPU/GlobalISel: Fix misuse of div_scale intrinsicsMatt Arsenault2019-12-211-5/+5
* AMDGPU/GlobalISel: Fix missing scc imp-def on scalar and/or/xorMatt Arsenault2019-12-211-0/+5
* AMDGPU/GlobalISel: Simplify codeMatt Arsenault2019-12-211-5/+5
* [WebAssembly] Use TargetIndex operands in DbgValue to track WebAssembly opera...Yury Delendik2019-12-206-0/+33
* Add parentheses to silence warningBill Wendling2019-12-201-2/+2
* More style cleanups following rG14fc20ca6282 [NFC]Philip Reames2019-12-201-34/+28
* Fix a memory leak introduced w/the instruction padding support in rG14fc20ca6282Philip Reames2019-12-201-6/+6
* Align branches within 32-Byte boundary (NOP padding)Philip Reames2019-12-201-1/+286
* [PPC32] Emit R_PPC_PLTREL24 for calls to dso_local ifuncFangrui Song2019-12-201-2/+3
* [X86] Fix a KNL miscompile caused by combineSetCC swapping LHS/RHS variables ...Craig Topper2019-12-201-19/+23
* [AArch64][SVE] Replace integer immediate intrinsics with splat vector variantDanilo Carvalho Grael2019-12-202-22/+39
* [SystemZ] Add a mapping from "select register" to "load on condition" (2-addr).Jonas Paulsson2019-12-204-81/+60
* [SystemZ] Bugfix and improve the handling of CC values.Jonas Paulsson2019-12-206-33/+141
* Revert "[ARM] Improve codegen of volatile load/store of i64"Victor Campos2019-12-206-158/+6
* [SystemZ][FPEnv] Enable strict vector FP extends/truncationsUlrich Weigand2019-12-204-13/+66
* [AArch64][SVE] Correct intrinsics and patterns for logical predicate instruct...Paul Walker2019-12-201-17/+17
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