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| author | Cullen Rhodes <cullen.rhodes@arm.com> | 2019-12-13 16:32:35 +0000 |
|---|---|---|
| committer | Cullen Rhodes <cullen.rhodes@arm.com> | 2019-12-19 11:03:32 +0000 |
| commit | eca0c97a6bca49b493f3387dbd88ad60c852320f (patch) | |
| tree | f1e2c03adf20f954302a0cc37f1867d2505a2306 /llvm/lib/Target | |
| parent | 49199465a3b21d86a871cb3d368b223c726f8aff (diff) | |
| download | bcm5719-llvm-eca0c97a6bca49b493f3387dbd88ad60c852320f.tar.gz bcm5719-llvm-eca0c97a6bca49b493f3387dbd88ad60c852320f.zip | |
[AArch64][SVE] Implement pfirst and pnext intrinsics
Reviewers: sdesmalen, efriedma, dancgr, mgudim, cameron.mcinally
Reviewed By: cameron.mcinally
Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl,
llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D71472
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/SVEInstrFormats.td | 13 |
2 files changed, 12 insertions, 5 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 2a282d320fe..92bc59a3b72 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -295,8 +295,8 @@ let Predicates = [HasSVE] in { def PTEST_PP : sve_int_ptest<0b010000, "ptest">; def PFALSE : sve_int_pfalse<0b000000, "pfalse">; - defm PFIRST : sve_int_pfirst<0b00000, "pfirst">; - defm PNEXT : sve_int_pnext<0b00110, "pnext">; + defm PFIRST : sve_int_pfirst<0b00000, "pfirst", int_aarch64_sve_pfirst>; + defm PNEXT : sve_int_pnext<0b00110, "pnext", int_aarch64_sve_pnext>; defm AND_PPzPP : sve_int_pred_log<0b0000, "and", int_aarch64_sve_and>; defm BIC_PPzPP : sve_int_pred_log<0b0001, "bic", int_aarch64_sve_bic>; diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index 99070b21480..63214215add 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -419,15 +419,22 @@ class sve_int_pfirst_next<bits<2> sz8_64, bits<5> opc, string asm, let Defs = [NZCV]; } -multiclass sve_int_pfirst<bits<5> opc, string asm> { - def : sve_int_pfirst_next<0b01, opc, asm, PPR8>; +multiclass sve_int_pfirst<bits<5> opc, string asm, SDPatternOperator op> { + def _B : sve_int_pfirst_next<0b01, opc, asm, PPR8>; + + def : SVE_2_Op_Pat<nxv16i1, op, nxv16i1, nxv16i1, !cast<Instruction>(NAME # _B)>; } -multiclass sve_int_pnext<bits<5> opc, string asm> { +multiclass sve_int_pnext<bits<5> opc, string asm, SDPatternOperator op> { def _B : sve_int_pfirst_next<0b00, opc, asm, PPR8>; def _H : sve_int_pfirst_next<0b01, opc, asm, PPR16>; def _S : sve_int_pfirst_next<0b10, opc, asm, PPR32>; def _D : sve_int_pfirst_next<0b11, opc, asm, PPR64>; + + def : SVE_2_Op_Pat<nxv16i1, op, nxv16i1, nxv16i1, !cast<Instruction>(NAME # _B)>; + def : SVE_2_Op_Pat<nxv8i1, op, nxv8i1, nxv8i1, !cast<Instruction>(NAME # _H)>; + def : SVE_2_Op_Pat<nxv4i1, op, nxv4i1, nxv4i1, !cast<Instruction>(NAME # _S)>; + def : SVE_2_Op_Pat<nxv2i1, op, nxv2i1, nxv2i1, !cast<Instruction>(NAME # _D)>; } //===----------------------------------------------------------------------===// |
