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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2019-12-20 21:39:19 +0530 |
|---|---|---|
| committer | Matt Arsenault <arsenm2@gmail.com> | 2019-12-21 04:55:36 -0500 |
| commit | 42a26445f9e68d55bcc4b8d1b4ced83a56d7743c (patch) | |
| tree | fe2acb04784c9e2617a687d09cdb4f119346d7ab /llvm/lib/Target | |
| parent | dff3f8d74240144c35e78978a73646aa34faf400 (diff) | |
| download | bcm5719-llvm-42a26445f9e68d55bcc4b8d1b4ced83a56d7743c.tar.gz bcm5719-llvm-42a26445f9e68d55bcc4b8d1b4ced83a56d7743c.zip | |
AMDGPU/GlobalISel: Fix misuse of div_scale intrinsics
Confusingly, the intrinsic operands do not match the
instruction/custom node. The order is shuffled, and the 3rd operand is
an immediate to select operands.
I'm not 100% sure I did this right, but fdiv still doesn't select end
to end and it will be easier to tell when it does. This at least
avoids an assertion in RegBankSelect and allows hitting the fallback
on selection.
Diffstat (limited to 'llvm/lib/Target')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index c21102fd611..055bde28cd5 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -2028,14 +2028,14 @@ bool AMDGPULegalizerInfo::legalizeFDIV32(MachineInstr &MI, auto DenominatorScaled = B.buildIntrinsic(Intrinsic::amdgcn_div_scale, {S32, S1}, false) .addUse(RHS) - .addUse(RHS) .addUse(LHS) + .addImm(1) .setMIFlags(Flags); auto NumeratorScaled = B.buildIntrinsic(Intrinsic::amdgcn_div_scale, {S32, S1}, false) .addUse(LHS) .addUse(RHS) - .addUse(LHS) + .addImm(0) .setMIFlags(Flags); auto ApproxRcp = B.buildIntrinsic(Intrinsic::amdgcn_rcp, {S32}, false) @@ -2091,9 +2091,9 @@ bool AMDGPULegalizerInfo::legalizeFDIV64(MachineInstr &MI, auto One = B.buildFConstant(S64, 1.0); auto DivScale0 = B.buildIntrinsic(Intrinsic::amdgcn_div_scale, {S64, S1}, false) - .addUse(RHS) - .addUse(RHS) .addUse(LHS) + .addUse(RHS) + .addImm(1) .setMIFlags(Flags); auto NegDivScale0 = B.buildFNeg(S64, DivScale0.getReg(0), Flags); @@ -2109,7 +2109,7 @@ bool AMDGPULegalizerInfo::legalizeFDIV64(MachineInstr &MI, auto DivScale1 = B.buildIntrinsic(Intrinsic::amdgcn_div_scale, {S64, S1}, false) .addUse(LHS) .addUse(RHS) - .addUse(LHS) + .addImm(0) .setMIFlags(Flags); auto Fma3 = B.buildFMA(S64, Fma1, Fma2, Fma1, Flags); |
