summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Expand)AuthorAgeFilesLines
* AMDGPU: Relax SGPR asm constraint register classMatt Arsenault2016-08-301-1/+1
* [AMDGPU] Refactor SOP instructions TD files.Valery Pykhtin2016-08-304-914/+1105
* SILoadStoreOptimizer.cpp: Fix a warning in r279991. [-Wunused-variable]NAKAMURA Takumi2016-08-301-0/+1
* Replace incorrect "#ifdef DEBUG" with "#ifndef NDEBUG".James Y Knight2016-08-301-11/+15
* [PowerPC] Force entry alignment in .got2Hal Finkel2016-08-301-2/+4
* [PowerPC] Add support for -mlongcallHal Finkel2016-08-304-1/+15
* ADT: Give ilist<T>::reverse_iterator a handle to the current nodeDuncan P. N. Exon Smith2016-08-302-7/+7
* AMDGPU/R600: Cleanup DAGCombineJan Vesely2016-08-291-15/+12
* Fix typo in comment. NFC.Michael Kuperstein2016-08-291-1/+1
* [PowerPC] Fix i8/i16 atomics for little-Endian targets without partword atomicsHal Finkel2016-08-291-6/+12
* AMDGPU/R600: Remove MergeVectorStores from legalizationJan Vesely2016-08-293-65/+0
* AMDGPU: fix mismatch tags, NFCSaleem Abdulrasool2016-08-292-2/+2
* [Myriad]: add missing 'mcpu' valuesDouglas Katzman2016-08-291-0/+3
* AMDGPU/SI: Implement a custom MachineSchedStrategyTom Stellard2016-08-299-1/+445
* AMDGPU/SI: Improve SILoadStoreOptimizer and run it before the schedulerTom Stellard2016-08-292-111/+148
* GlobalISel: legalize frem to a libcall on AArch64.Tim Northover2016-08-293-2/+5
* GlobalISel: rework CallLowering so that it can be used for libcalls too.Tim Northover2016-08-292-19/+11
* AMDGPU/R600: Fix fixups used for constant arraysMatt Arsenault2016-08-291-0/+1
* [AArch64] Adjust the scheduling model for Exynos M1.Evandro Menezes2016-08-291-4/+14
* AMDGPU/SI: Improve register allocation hints for sopk instructionsTom Stellard2016-08-291-0/+1
* Fix -Wunused-but-set-variable warning.Haojian Wu2016-08-291-4/+0
* AMDGPU/SI: Query AA, if available, in areMemAccessesTriviallyDisjoint()Tom Stellard2016-08-291-0/+11
* [AVX512] In some cases KORTEST instruction may be used instead of ZEXT + TEST...Igor Breger2016-08-292-5/+23
* [X86] Don't lower FABS/FNEG masking directly to a ConstantPool load. Just cre...Craig Topper2016-08-291-9/+4
* [AVX-512] Always use v8i64 when converting 512-bit FAND/FOR/FXOR/FANDN to int...Craig Topper2016-08-291-5/+3
* [AVX-512] Add support for selecting 512-bit VPABSB/VPABSW when BWI is available.Craig Topper2016-08-282-2/+19
* [AVX-512] Add patterns for selecting 128/256-bit EVEX VPABS instructions.Craig Topper2016-08-282-2/+37
* [X86][AVX512] Only combine EVEX targets shuffles to shuffles of the same numb...Simon Pilgrim2016-08-281-4/+12
* [PowerPC] Implement lowering for atomicrmw min/max/umin/umaxHal Finkel2016-08-284-5/+152
* [AVX-512] Promote AND/OR/XOR to v2i64/v4i64/v8i64 even when we have AVX512F/A...Craig Topper2016-08-282-18/+124
* [X86] Rename PABSB/D/W instructions to be consistent with SSE/AVX instruction...Craig Topper2016-08-282-40/+40
* AMDGPU/R600: Enable Load combineJan Vesely2016-08-271-0/+1
* [X86] Rename predicate function that detects if requires one of the REX.B, RE...Craig Topper2016-08-271-15/+16
* [X86] Keep looping over operands looking for byte registers even if we alread...Craig Topper2016-08-271-5/+4
* [X86] Include XMM/YMM/ZMM16-23 in X86II::isX86_64ExtendedReg. This feels more...Craig Topper2016-08-272-8/+4
* [X86] Don't allow DR8-DR15 to be assembled in 32-bit mode. Add missing test f...Craig Topper2016-08-271-0/+2
* [X86] Remove stale comment about FixupBWInsts pass being off by default. NFCCraig Topper2016-08-271-2/+0
* [AVX-512] Allow EVEX encoding unordered/ordered/equal/notequal VCMPPS/PD/SS/S...Craig Topper2016-08-272-8/+28
* [X86] Enable FR32/FR64 cmpeq/cmpne/cmpunord/cmpord to be commuted.Craig Topper2016-08-272-0/+9
* [AVX-512] Add load folding for EVEX vcmpps/pd/ss/sd.Craig Topper2016-08-271-0/+8
* AMDGPU: Mark sched model completeMatt Arsenault2016-08-271-1/+1
* AMDGPU: Remove unneeded implicit exec uses/defsMatt Arsenault2016-08-272-40/+48
* AMDGPU: Select mulhi 24-bit instructionsMatt Arsenault2016-08-277-20/+163
* AMDGPU: Move cndmask pseudo to be isel pseudoMatt Arsenault2016-08-273-23/+31
* AMDGPU: Fix sched type for branchesMatt Arsenault2016-08-271-1/+1
* AMDGPU: Remove register operand from si_mask_branchMatt Arsenault2016-08-272-5/+3
* AMDGPU: Improve error reporting for maximum branch distanceMatt Arsenault2016-08-271-30/+61
* [AArch64][CallLowering] Do not assert for not implemented part.Quentin Colombet2016-08-271-6/+9
* AMDGPU/SI: Canonicalize offset order for merged DS instructionsTom Stellard2016-08-261-3/+15
* XXXTom Stellard2016-08-261-1/+1
OpenPOWER on IntegriCloud