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path: root/llvm/lib/Target/X86/X86Subtarget.cpp
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* [X86] Convert PICStyles::Style to scoped enum class. NFCI.Simon Pilgrim2019-11-031-7/+7
* [Alignment][NFC] Use Align for TargetFrameLowering/SubtargetGuillaume Chatelet2019-10-171-6/+5
* [X86] Add prefer-128-bit subtarget feature.Craig Topper2019-09-071-0/+2
* [TargetMachine] Don't try to create COFFSTUB references on windows on non-COFFMartin Storsjo2019-08-201-0/+3
* [GlobalISel] Make the InstructionSelector instance non-const, allowing state ...Amara Emerson2019-08-131-1/+1
* [COFF] Use COFF stubs for extern_weak functionsReid Kleckner2019-05-071-3/+6
* [X86] Make post-ra scheduling macrofusion-aware.Clement Courbet2019-04-011-0/+6
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [MinGW] Move code for indicating "potentially not DSO local" into shouldAssum...Martin Storsjo2018-09-041-10/+5
* [X86] Make Feature64Bit usefulCraig Topper2018-08-301-6/+15
* [MinGW] [X86] Add stubs for references to data variables that might end up im...Martin Storsjo2018-08-291-0/+8
* [AArch64] Add Tiny Code Model for AArch64David Green2018-08-221-0/+2
* Re-land r335297 "[X86] Implement more of x86-64 large and medium PIC code mod...Reid Kleckner2018-07-231-8/+36
* Revert "Re-land r335297 "[X86] Implement more of x86-64 large and medium PIC ...Jonas Devlieghere2018-06-281-25/+9
* Re-land r335297 "[X86] Implement more of x86-64 large and medium PIC code mod...Reid Kleckner2018-06-251-9/+25
* Revert r335297 "[X86] Implement more of x86-64 large and medium PIC code models"Reid Kleckner2018-06-211-24/+8
* [X86] Implement more of x86-64 large and medium PIC code modelsReid Kleckner2018-06-211-8/+24
* [X86] NFC Use member initialization in X86SubtargetGabor Buella2018-06-091-110/+1
* [x86] invpcid LLVM intrinsicGabor Buella2018-05-251-0/+1
* [X86][CET] Changing -fcf-protection behavior to comply with gcc (LLVM part)Alexander Ivchenko2018-05-181-1/+0
* Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen2018-05-141-3/+3
* [X86] Initialize HasPTWRITE member of X86SubtargetGabor Buella2018-05-101-0/+1
* [x86] Introduce the pconfig instructionGabor Buella2018-05-081-0/+1
* [X86] movdiri and movdir64b instructionsGabor Buella2018-05-011-0/+2
* [X86] Revert r330638 - accidental commitGabor Buella2018-04-231-2/+0
* [X86] movdiri and movdir64b instructionsGabor Buella2018-04-231-0/+2
* [X86] WaitPKG instructionsGabor Buella2018-04-201-0/+1
* [X86] Remove remaining itinerary support from instructions and target (PR37093)Simon Pilgrim2018-04-131-2/+0
* [X86] Introduce cldemote instructionGabor Buella2018-04-131-0/+1
* [X86] Describe wbnoinvd instructionGabor Buella2018-04-111-0/+1
* Intrinsics calls should avoid the PLT when "RtLibUseGOT" metadata is present.Sriraman Tallam2018-02-231-2/+5
* [X86] Don't make 512-bit vectors legal when preferred vector width is 256 bit...Craig Topper2018-02-111-1/+3
* [X86] Emit 11-byte or 15-byte NOPs on recent AMD targets, else default to 10-...Simon Pilgrim2018-01-291-0/+2
* Introduce the "retpoline" x86 mitigation technique for variant #2 of the spec...Chandler Carruth2018-01-221-0/+2
* Break false dependencies for POPCNT, LZCNT, TZCNTMarina Yatsina2018-01-221-0/+2
* [X86] Add support for passing 'prefer-vector-width' function attribute into X...Craig Topper2018-01-201-1/+11
* [X86] Add intrinsic support for the RDPID instructionCraig Topper2018-01-181-0/+1
* [X86] Move HasNOPL to a subtarget feature bit. Plumb MCSubtargetInfo through ...Craig Topper2018-01-101-0/+1
* [X86] Add missing initialization for the HasPREFETCHWT1 subtarget variable.Craig Topper2017-12-221-0/+1
* [X86] Fix uninitialized variable sanitizer warning from rL321074Simon Pilgrim2017-12-191-0/+1
* X86/AArch64/ARM: Factor out common sincos_stret logic; NFCIMatthias Braun2017-12-181-9/+0
* AArch64/X86: Factor out common bzero logic; NFCMatthias Braun2017-12-181-13/+0
* Remove redundant includes from lib/Target/X86.Michael Zolotukhin2017-12-131-4/+0
* Control-Flow Enforcement Technology - Shadow Stack support (LLVM side)Oren Ben Simhon2017-11-261-0/+2
* [x86][icelake]GFNICoby Tayree2017-11-261-0/+1
* [X86] Don't report gather is legal on Skylake CPUs when AVX2/AVX512 is disabl...Craig Topper2017-11-251-6/+6
* [x86][icelake]BITALGCoby Tayree2017-11-211-0/+1
* [x86][icelake]VNNICoby Tayree2017-11-211-0/+1
* [x86][icelake]vbmi2Coby Tayree2017-11-211-0/+1
* [x86][icelake]vpclmulqdq introductionCoby Tayree2017-11-211-0/+1
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