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| author | Oren Ben Simhon <oren.ben.simhon@intel.com> | 2017-11-26 13:02:45 +0000 |
|---|---|---|
| committer | Oren Ben Simhon <oren.ben.simhon@intel.com> | 2017-11-26 13:02:45 +0000 |
| commit | fa582b075c4762829eea59444624c9d90e6b1113 (patch) | |
| tree | ace7d05b3f111e55b451061d5b61cfd34b3340aa /llvm/lib/Target/X86/X86Subtarget.cpp | |
| parent | fec21ec0c6257eb24290c483b03b4fd9e6a9d0d1 (diff) | |
| download | bcm5719-llvm-fa582b075c4762829eea59444624c9d90e6b1113.tar.gz bcm5719-llvm-fa582b075c4762829eea59444624c9d90e6b1113.zip | |
Control-Flow Enforcement Technology - Shadow Stack support (LLVM side)
Shadow stack solution introduces a new stack for return addresses only.
The HW has a Shadow Stack Pointer (SSP) that points to the next return address.
If we return to a different address, an exception is triggered.
The shadow stack is managed using a series of intrinsics that are introduced in this patch as well as the new register (SSP).
The intrinsics are mapped to new instruction set that implements CET mechanism.
The patch also includes initial infrastructure support for IBT.
For more information, please see the following:
https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf
Differential Revision: https://reviews.llvm.org/D40223
Change-Id: I4daa1f27e88176be79a4ac3b4cd26a459e88fed4
llvm-svn: 318996
Diffstat (limited to 'llvm/lib/Target/X86/X86Subtarget.cpp')
| -rw-r--r-- | llvm/lib/Target/X86/X86Subtarget.cpp | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/llvm/lib/Target/X86/X86Subtarget.cpp b/llvm/lib/Target/X86/X86Subtarget.cpp index 72c08e21799..963a9c30de0 100644 --- a/llvm/lib/Target/X86/X86Subtarget.cpp +++ b/llvm/lib/Target/X86/X86Subtarget.cpp @@ -334,6 +334,8 @@ void X86Subtarget::initializeEnvironment() { HasMWAITX = false; HasCLZERO = false; HasMPX = false; + HasSHSTK = false; + HasIBT = false; HasSGX = false; HasCLFLUSHOPT = false; HasCLWB = false; |
