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path: root/llvm/lib/Target/X86/X86SchedSkylakeClient.td
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* [X86][BtVer2] Fix latency and throughput of conditional SIMD store instructions.Andrea Di Biagio2019-09-021-2/+6
* [X86] Add zero idioms to the haswell, broadwell, and skylake schedule models....Craig Topper2019-05-251-4/+96
* [X86] Merge the different SETcc instructions for each condition code into sin...Craig Topper2019-04-051-14/+26
* [X86] Merge the different CMOV instructions for each condition code into sing...Craig Topper2019-04-051-1/+26
* [X86] Correct scheduler information for rotate by constant for Haswell, Broad...Craig Topper2019-03-071-1/+9
* [X86] Correct some ADC/SBB with immediate scheduler data for Broadwell and Sk...Craig Topper2019-02-241-3/+4
* [MC][X86] Correctly model additional operand latency caused by transfer delay...Andrea Di Biagio2019-01-231-0/+2
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [X86] Fix VZEROUPPER scheduling info on SNB,HSW,BDW,SXL,SKX.Clement Courbet2018-11-091-3/+3
* [X86] Fix Skylake ReadAfterLd for PADDrm etc.Simon Pilgrim2018-10-161-2/+4
* [X86] Move ReadAfterLd functionality into X86FoldableSchedWrite (PR36957)Simon Pilgrim2018-10-051-1/+7
* [X86] Remove unnecessary BT(C/R/S)m(i/r) scheduler overridesSimon Pilgrim2018-10-021-5/+2
* [X86] Create schedule classes for BT(C|R|S)mi and BT(C|R|S)mr instructionsSimon Pilgrim2018-10-011-5/+7
* [X86] Remove unnecessary BTmi/BTmr scheduler overridesSimon Pilgrim2018-10-011-7/+0
* [X86] Create schedule classes for BTmi and BTmr instructionsSimon Pilgrim2018-10-011-3/+6
* [X86] Split BT and BTC/BTR/BTS scheduler classesSimon Pilgrim2018-09-271-2/+3
* Revert rL342916: [X86] Remove shift/rotate by CL memory (RMW) overridesSimon Pilgrim2018-09-251-6/+17
* [X86] Remove shift/rotate by CL memory (RMW) overridesSimon Pilgrim2018-09-241-17/+6
* [X86] Remove WriteDiv/WriteIDiv schedule overrides - use classes directly. NFCI.Simon Pilgrim2018-09-241-29/+17
* [X86] Split WriteIMul into 8/16/32/64 implementations (PR36931)Simon Pilgrim2018-09-241-59/+14
* [X86] Split WriteShift/WriteRotate schedule classes by CL usage.Simon Pilgrim2018-09-231-13/+4
* [X86] ROR*mCL instruction models should match ROL*mCL etc.Simon Pilgrim2018-09-231-7/+1
* [X86] Remove unnecessary WriteRotate overrides. NFCI.Simon Pilgrim2018-09-231-4/+2
* [X86] Add WriteRotate schedule class, splitting off from WriteShift.Simon Pilgrim2018-09-231-1/+2
* [X86][BMI1] Add scheduler class for BLSI/BLSMSK/BLSR BMI1 instructionsSimon Pilgrim2018-09-141-9/+4
* [X86] Improved sched model for X86 CMPXCHG* instructions.Andrew V. Tischenko2018-08-301-8/+2
* [X86] Replace all single match schedule class instregexs with instrs entriesSimon Pilgrim2018-08-181-110/+109
* [X86] Merge shift/rotate schedule class instregexsSimon Pilgrim2018-08-181-22/+11
* [X86] Improved sched models for X86 XCHG*rr and XADD*rr instructions.Andrew V. Tischenko2018-08-091-9/+1
* [X86] Improved sched models for X86 BT*rr instructions.Andrew V. Tischenko2018-08-011-8/+1
* [X86] WriteBSWAP sched classes are reg-reg only.Simon Pilgrim2018-07-311-2/+2
* Revert r338365: [X86] Improved sched models for X86 BT*rr instructions.Simon Pilgrim2018-07-311-1/+8
* [X86] Improved sched models for X86 BT*rr instructions.Andrew V. Tischenko2018-07-311-8/+1
* [X86] Improved sched models for X86 SHLD/SHRD* instructions.Andrew V. Tischenko2018-07-311-29/+6
* Improved sched model for X86 BSWAP* instrs.Andrew V. Tischenko2018-07-201-14/+3
* [X86][Nearly NFC] Split SHLD/SHRD into their own WriteShiftDouble classRoman Lebedev2018-07-081-0/+3
* [X86][Basically NFC] Sched: split WriteBitScan into WriteBSF/WriteBSR.Roman Lebedev2018-07-081-4/+5
* [X86] Add sched class WriteLAHFSAHF and fix values.Clement Courbet2018-06-201-1/+1
* [X86] Fix NOOP sched overrides on BDW/HSW/SKL.Clement Courbet2018-06-181-2/+1
* [X86] Fix skylake server scheduling info.Clement Courbet2018-06-111-56/+97
* [X86] Explicitly mark unsupported classes in scheduling models.Clement Courbet2018-06-111-4/+4
* [X86] Introduce WriteFLDC for x87 constant loads.Clement Courbet2018-05-311-0/+1
* [X86] Extract latency of fldz/fld1 in separate classes.Clement Courbet2018-05-311-0/+2
* [X86][Sched] Add InstRW for CLC on Intel after SNB.Clement Courbet2018-05-291-1/+3
* [X86] Add GPR<->XMM Schedule TagsSimon Pilgrim2018-05-181-17/+4
* [X86][SSE] Ensure vector partial load/stores use the WriteVecLoad/WriteVecSto...Simon Pilgrim2018-05-181-6/+0
* [X86] Split WriteCMOV + WriteCMOV2 scheduler classesSimon Pilgrim2018-05-171-10/+3
* [X86] Split WriteADC/WriteADCRMW scheduler classesSimon Pilgrim2018-05-171-19/+5
* [X86] Split WriteCvtI2F/WriteCvtF2I into I<->F32 and I<->F64 scheduler classesSimon Pilgrim2018-05-161-3/+13
* [X86] Split WriteCvtF2F into F32->F64 and F64->F32 scheduler classesSimon Pilgrim2018-05-151-1/+8
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