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| author | Andrew V. Tischenko <andrew.v.tischenko@gmail.com> | 2018-07-20 09:39:14 +0000 |
|---|---|---|
| committer | Andrew V. Tischenko <andrew.v.tischenko@gmail.com> | 2018-07-20 09:39:14 +0000 |
| commit | ee2e3144ba5794e9d978eee98bb88d19f5b47f47 (patch) | |
| tree | 085cc4c60db72d17b4f29ac7988c963e0235714b /llvm/lib/Target/X86/X86SchedSkylakeClient.td | |
| parent | 12be7b7bf7308aed4288419154d5227f11a441cf (diff) | |
| download | bcm5719-llvm-ee2e3144ba5794e9d978eee98bb88d19f5b47f47.tar.gz bcm5719-llvm-ee2e3144ba5794e9d978eee98bb88d19f5b47f47.zip | |
Improved sched model for X86 BSWAP* instrs.
Differential Revision: https://reviews.llvm.org/D49477
llvm-svn: 337537
Diffstat (limited to 'llvm/lib/Target/X86/X86SchedSkylakeClient.td')
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedSkylakeClient.td | 17 |
1 files changed, 3 insertions, 14 deletions
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td index a59d2c459ee..1417799d76b 100644 --- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td +++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td @@ -110,6 +110,9 @@ defm : SKLWriteResPair<WriteADC, [SKLPort06], 1>; // Integer ALU + flags op defm : SKLWriteResPair<WriteIMul, [SKLPort1], 3>; // Integer multiplication. defm : SKLWriteResPair<WriteIMul64, [SKLPort1], 3>; // Integer 64-bit multiplication. +defm : SKLWriteResPair<WriteBSWAP32,[SKLPort15], 1>; // +defm : SKLWriteResPair<WriteBSWAP64,[SKLPort06, SKLPort15], 2, [1,1], 2>; // + defm : SKLWriteResPair<WriteDiv8, [SKLPort0, SKLDivider], 25, [1,10], 1, 4>; defm : SKLWriteResPair<WriteDiv16, [SKLPort0, SKLDivider], 25, [1,10], 1, 4>; defm : SKLWriteResPair<WriteDiv32, [SKLPort0, SKLDivider], 25, [1,10], 1, 4>; @@ -698,20 +701,6 @@ def SKLWriteResGroup21 : SchedWriteRes<[SKLPort237,SKLPort0156]> { } def: InstRW<[SKLWriteResGroup21], (instrs SFENCE)>; -def SKLWriteResGroup22 : SchedWriteRes<[SKLPort06,SKLPort15]> { - let Latency = 2; - let NumMicroOps = 2; - let ResourceCycles = [1,1]; -} -def: InstRW<[SKLWriteResGroup22], (instrs BSWAP64r)>; - -def SKLWriteResGroup22_1 : SchedWriteRes<[SKLPort15]> { - let Latency = 1; - let NumMicroOps = 1; - let ResourceCycles = [1]; -} -def: InstRW<[SKLWriteResGroup22_1], (instrs BSWAP32r)>; - def SKLWriteResGroup23 : SchedWriteRes<[SKLPort06,SKLPort0156]> { let Latency = 2; let NumMicroOps = 2; |
