| Commit message (Expand) | Author | Age | Files | Lines |
|---|
| * | [X86][BtVer2] Fix latency and throughput of conditional SIMD store instructions. | Andrea Di Biagio | 2019-09-02 | 1 | -2/+6 |
| * | [X86] Add zero idioms to the haswell, broadwell, and skylake schedule models.... | Craig Topper | 2019-05-25 | 1 | -7/+13 |
| * | [X86] Merge the different SETcc instructions for each condition code into sin... | Craig Topper | 2019-04-05 | 1 | -14/+26 |
| * | [X86] Merge the different CMOV instructions for each condition code into sing... | Craig Topper | 2019-04-05 | 1 | -1/+26 |
| * | [MC][X86] Correctly model additional operand latency caused by transfer delay... | Andrea Di Biagio | 2019-01-23 | 1 | -0/+2 |
| * | Update the file headers across all of the LLVM projects in the monorepo | Chandler Carruth | 2019-01-19 | 1 | -4/+3 |
| * | [X86] Fix VZEROUPPER scheduling info on SNB,HSW,BDW,SXL,SKX. | Clement Courbet | 2018-11-09 | 1 | -0/+7 |
| * | [X86] Move ReadAfterLd functionality into X86FoldableSchedWrite (PR36957) | Simon Pilgrim | 2018-10-05 | 1 | -1/+7 |
| * | [X86] Remove unnecessary BT(C/R/S)m(i/r) scheduler overrides | Simon Pilgrim | 2018-10-02 | 1 | -8/+5 |
| * | [X86] Create schedule classes for BT(C|R|S)mi and BT(C|R|S)mr instructions | Simon Pilgrim | 2018-10-01 | 1 | -5/+7 |
| * | [X86] Remove unnecessary BTmi/BTmr scheduler overrides | Simon Pilgrim | 2018-10-01 | 1 | -9/+2 |
| * | [X86] Create schedule classes for BTmi and BTmr instructions | Simon Pilgrim | 2018-10-01 | 1 | -3/+6 |
| * | [X86][Sched] Update scheduling information for VZEROALL on HWS, BDW, SKX, SNB. | Clement Courbet | 2018-10-01 | 1 | -0/+7 |
| * | [X86] Split BT and BTC/BTR/BTS scheduler classes | Simon Pilgrim | 2018-09-27 | 1 | -2/+3 |
| * | Revert rL342916: [X86] Remove shift/rotate by CL memory (RMW) overrides | Simon Pilgrim | 2018-09-25 | 1 | -7/+29 |
| * | [X86] Remove shift/rotate by CL memory (RMW) overrides | Simon Pilgrim | 2018-09-24 | 1 | -29/+7 |
| * | [X86] Split WriteIMul into 8/16/32/64 implementations (PR36931) | Simon Pilgrim | 2018-09-24 | 1 | -61/+14 |
| * | [X86] Split WriteShift/WriteRotate schedule classes by CL usage. | Simon Pilgrim | 2018-09-23 | 1 | -13/+4 |
| * | [X86] Remove unnecessary WriteRotate override. NFCI. | Simon Pilgrim | 2018-09-23 | 1 | -4/+2 |
| * | Fix line ending mismatches. NFCI. | Simon Pilgrim | 2018-09-23 | 1 | -6/+6 |
| * | [X86] Added missing RCL/RCR schedule overrides to the generic SNB model | Simon Pilgrim | 2018-09-23 | 1 | -0/+24 |
| * | [X86] Add WriteRotate schedule class, splitting off from WriteShift. | Simon Pilgrim | 2018-09-23 | 1 | -1/+3 |
| * | [X86][Sched] Add zero idiom sched data to the SNB model. | Clement Courbet | 2018-09-21 | 1 | -1/+51 |
| * | [X86][BMI1] Add scheduler class for BLSI/BLSMSK/BLSR BMI1 instructions | Simon Pilgrim | 2018-09-14 | 1 | -2/+3 |
| * | [X86] Improved sched model for X86 CMPXCHG* instructions. | Andrew V. Tischenko | 2018-08-30 | 1 | -13/+8 |
| * | [X86] Replace all single match schedule class instregexs with instrs entries | Simon Pilgrim | 2018-08-18 | 1 | -34/+35 |
| * | [X86] Merge shift/rotate schedule class instregexs | Simon Pilgrim | 2018-08-18 | 1 | -14/+7 |
| * | [X86] Improved sched models for X86 XCHG*rr and XADD*rr instructions. | Andrew V. Tischenko | 2018-08-09 | 1 | -9/+1 |
| * | [X86] Improved sched models for X86 BT*rr instructions. | Andrew V. Tischenko | 2018-08-01 | 1 | -8/+1 |
| * | [X86] WriteBSWAP sched classes are reg-reg only. | Simon Pilgrim | 2018-07-31 | 1 | -2/+2 |
| * | Revert r338365: [X86] Improved sched models for X86 BT*rr instructions. | Simon Pilgrim | 2018-07-31 | 1 | -1/+8 |
| * | [X86] Improved sched models for X86 BT*rr instructions. | Andrew V. Tischenko | 2018-07-31 | 1 | -8/+1 |
| * | [X86] Improved sched models for X86 SHLD/SHRD* instructions. | Andrew V. Tischenko | 2018-07-31 | 1 | -33/+7 |
| * | Improved sched model for X86 BSWAP* instrs. | Andrew V. Tischenko | 2018-07-20 | 1 | -14/+3 |
| * | [X86][Nearly NFC] Split SHLD/SHRD into their own WriteShiftDouble class | Roman Lebedev | 2018-07-08 | 1 | -0/+1 |
| * | [X86][Basically NFC] Sched: split WriteBitScan into WriteBSF/WriteBSR. | Roman Lebedev | 2018-07-08 | 1 | -4/+5 |
| * | [X86] Add sched class WriteLAHFSAHF and fix values. | Clement Courbet | 2018-06-20 | 1 | -1/+1 |
| * | [X86] Fix skylake server scheduling info. | Clement Courbet | 2018-06-11 | 1 | -0/+45 |
| * | [X86] Explicitly mark unsupported classes in scheduling models. | Clement Courbet | 2018-06-11 | 1 | -4/+8 |
| * | [X86] Introduce WriteFLDC for x87 constant loads. | Clement Courbet | 2018-05-31 | 1 | -0/+1 |
| * | [X86] Extract latency of fldz/fld1 in separate classes. | Clement Courbet | 2018-05-31 | 1 | -0/+2 |
| * | [X86][Sched] Add InstRW for CLC on Intel after SNB. | Clement Courbet | 2018-05-29 | 1 | -0/+2 |
| * | [X86][SNB] Fix differences between vex/non-vex XMM vector moves (PR37286) | Simon Pilgrim | 2018-05-25 | 1 | -9/+1 |
| * | [X86] Add GPR<->XMM Schedule Tags | Simon Pilgrim | 2018-05-18 | 1 | -10/+2 |
| * | [X86] Split WriteCMOV + WriteCMOV2 scheduler classes | Simon Pilgrim | 2018-05-17 | 1 | -14/+1 |
| * | [X86] Split WriteADC/WriteADCRMW scheduler classes | Simon Pilgrim | 2018-05-17 | 1 | -17/+3 |
| * | [X86][SNB] Minor scheduler cleanup | Simon Pilgrim | 2018-05-17 | 1 | -7/+3 |
| * | [X86][SNB] Remove unnecessary CVT InstRW overrides | Simon Pilgrim | 2018-05-16 | 1 | -82/+24 |
| * | [X86] Split WriteCvtI2F/WriteCvtF2I into I<->F32 and I<->F64 scheduler classes | Simon Pilgrim | 2018-05-16 | 1 | -3/+13 |
| * | [X86] Split WriteCvtF2F into F32->F64 and F64->F32 scheduler classes | Simon Pilgrim | 2018-05-15 | 1 | -27/+16 |
