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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-09-23 21:19:15 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2018-09-23 21:19:15 +0000 |
| commit | f3f3dd584a6b72572e96454f47a20c382c98b23c (patch) | |
| tree | 6791b2ab5773854690070230c5cead12ba7ba865 /llvm/lib/Target/X86/X86SchedSandyBridge.td | |
| parent | b3b94a8e8b597b98cba58f88e681058ec4568d7d (diff) | |
| download | bcm5719-llvm-f3f3dd584a6b72572e96454f47a20c382c98b23c.tar.gz bcm5719-llvm-f3f3dd584a6b72572e96454f47a20c382c98b23c.zip | |
[X86] Split WriteShift/WriteRotate schedule classes by CL usage.
Variable Shifts/Rotates using the CL register have different behaviours to the immediate instructions - split accordingly to help remove yet more repeated overrides from the schedule models.
llvm-svn: 342852
Diffstat (limited to 'llvm/lib/Target/X86/X86SchedSandyBridge.td')
| -rw-r--r-- | llvm/lib/Target/X86/X86SchedSandyBridge.td | 17 |
1 files changed, 4 insertions, 13 deletions
diff --git a/llvm/lib/Target/X86/X86SchedSandyBridge.td b/llvm/lib/Target/X86/X86SchedSandyBridge.td index 740a5565162..e9725b799a5 100644 --- a/llvm/lib/Target/X86/X86SchedSandyBridge.td +++ b/llvm/lib/Target/X86/X86SchedSandyBridge.td @@ -135,8 +135,10 @@ defm : X86WriteRes<WriteSHDrrcl,[SBPort05, SBPort015], 4, [3, 1], 4>; defm : X86WriteRes<WriteSHDmri, [SBPort4,SBPort23,SBPort05,SBPort015], 8, [1, 2, 1, 1], 5>; defm : X86WriteRes<WriteSHDmrcl,[SBPort4,SBPort23,SBPort05,SBPort015], 10, [1, 2, 3, 1], 7>; -defm : SBWriteResPair<WriteShift, [SBPort05], 1>; -defm : SBWriteResPair<WriteRotate, [SBPort05], 2, [2], 2>; +defm : SBWriteResPair<WriteShift, [SBPort05], 1>; +defm : SBWriteResPair<WriteShiftCL, [SBPort05], 3, [3], 3>; +defm : SBWriteResPair<WriteRotate, [SBPort05], 2, [2], 2>; +defm : SBWriteResPair<WriteRotateCL, [SBPort05], 3, [3], 3>; defm : SBWriteResPair<WriteJump, [SBPort5], 1>; defm : SBWriteResPair<WriteCRC32, [SBPort1], 3, [1], 1, 5>; @@ -661,17 +663,6 @@ def SBWriteResGroup23 : SchedWriteRes<[SBPort05]> { def: InstRW<[SBWriteResGroup23], (instregex "RCL(8|16|32|64)r1", "RCR(8|16|32|64)r1")>; -def SBWriteResGroup23_2 : SchedWriteRes<[SBPort05]> { - let Latency = 3; - let NumMicroOps = 3; - let ResourceCycles = [3]; -} -def: InstRW<[SBWriteResGroup23_2], (instregex "ROL(8|16|32|64)rCL", - "ROR(8|16|32|64)rCL", - "SAR(8|16|32|64)rCL", - "SHL(8|16|32|64)rCL", - "SHR(8|16|32|64)rCL")>; - def SBWriteResGroup25_1 : SchedWriteRes<[SBPort23,SBPort015]> { let Latency = 7; let NumMicroOps = 3; |
