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path: root/llvm/lib/Target/X86/X86ISelLowering.cpp
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* [X86][SSE] Begin removing vector CTTZ custom lowering and use LegalizeDAG ins...Simon Pilgrim2018-10-131-9/+8
* [X86][SSE] combineIncDecVector - use isConstantSplatSimon Pilgrim2018-10-131-3/+1
* [X86] Pull out target constant splat helper function. NFCI.Simon Pilgrim2018-10-131-17/+27
* Pull out repeated getOperand(). NFCI.Simon Pilgrim2018-10-131-3/+2
* Remove unused variable. NFCI.Simon Pilgrim2018-10-131-1/+0
* [X86][SSE] Improve CTTZ lowering when CTLZ is legalSimon Pilgrim2018-10-131-11/+13
* [X86][SSE] Change CTTZ vector lowering to cttz(x) = ctpop(~x & (x - 1))Simon Pilgrim2018-10-131-8/+12
* [X86][AVX] Add lowerVectorShuffleAsLanePermuteAndPermute for v4f64 shuffles (...Simon Pilgrim2018-10-131-0/+60
* [X86] Improve type legalization of (v2i32/v4i16/v8i16 (bitcast (v2f32))) to a...Craig Topper2018-10-121-7/+13
* [X86] Simplify the end of custom type legalization for (v2i32/v4i16/v8i8 (bit...Craig Topper2018-10-121-7/+3
* [X86] Skip (v2i32/v4i16/v8i8 (bitcast (f64))) handling in ReplaceNodeResults ...Craig Topper2018-10-121-8/+2
* [x86] add and use fast horizontal vector math subtarget featureSanjay Patel2018-10-121-6/+16
* Fix unused variable warning after r344348Eric Liu2018-10-121-0/+1
* [X86][SSE] LowerVectorCTPOP - pull out repeated byte sum stage. Simon Pilgrim2018-10-121-51/+30
* [X86][SSE] Add extract_subvector(PSHUFB) -> PSHUFB(extract_subvector()) combineSimon Pilgrim2018-10-121-0/+12
* Inline variable into assert to avoid unused variable warning.Richard Trieu2018-10-111-2/+1
* [X86] Type legalize v2f32 loads by using an f64 load and a scalar_to_vector.Craig Topper2018-10-111-0/+24
* [X86] Restore X86ISelDAGToDAG::matchBEXTRFromAnd. Teach address matching to c...Craig Topper2018-10-111-66/+0
* [X86] Move X86DAGToDAGISel::matchBEXTRFromAnd() into X86ISelLoweringRoman Lebedev2018-10-101-0/+66
* [x86] allow single source horizontal op matching (PR39195)Sanjay Patel2018-10-101-2/+6
* [TargetLowering] Add root node back to work list after successful SimplifyDem...Simon Pilgrim2018-10-101-14/+2
* [X86] When lowering unsigned v2i64 setcc without SSE42, flip the sign bits in...Craig Topper2018-10-091-10/+8
* [x86] use demanded bits to simplify masked store codegenSanjay Patel2018-10-091-17/+16
* [X86][AVX1] Enable *_EXTEND_VECTOR_INREG lowering of 256-bit vectorsSimon Pilgrim2018-10-091-15/+34
* [X86] Prefer isTypeLegal over checking isSimple in a DAG combine.Craig Topper2018-10-081-1/+3
* [X86][AVX2] Enable ZERO_EXTEND_VECTOR_INREG lowering of 256-bit vectorsSimon Pilgrim2018-10-081-7/+5
* [x86] make horizontal binop matching clearer; NFCISanjay Patel2018-10-081-41/+37
* [X86] getFauxShuffleMask - Handle undef + sentinel values in subvector insertionSimon Pilgrim2018-10-061-1/+3
* [X86][AVX] Ensure resolveTargetShuffleInputs shuffle masks are the correct widthSimon Pilgrim2018-10-061-1/+2
* [X86] combinePMULDQ - add op back to worklist if SimplifyDemandedBits succeed...Simon Pilgrim2018-10-061-2/+6
* [X86][SSE] SimplifyDemandedVectorEltsForTargetNode - simplify PSHUFB masksSimon Pilgrim2018-10-061-0/+9
* [X86] Use the SimplifyDemandedBits wrappers where possible. NFCI.Simon Pilgrim2018-10-061-23/+4
* [X86][AVX] Limit getFauxShuffleMask INSERT_SUBVECTOR support to 2 inputsSimon Pilgrim2018-10-051-1/+2
* [X86] Don't promote i16 compares to i32 if the immediate will fit in 8 bits.Craig Topper2018-10-051-2/+5
* [X86][AVX] getFauxShuffleMask - add support for INSERT_SUBVECTOR subvector sh...Simon Pilgrim2018-10-051-0/+36
* [X86][LegalizeVectorOps] Use MERGE_VALUES to return two results from LowerLoa...Craig Topper2018-10-041-11/+6
* [X86] Set correct MMO offset on scalarized load piecesDavid Greene2018-10-041-3/+9
* [X86] Merge matchANDXORWithAllOnesAsANDNP into combineANDXORWithAllOnesIntoAN...Craig Topper2018-10-041-25/+12
* [X86] Stop promoting vector ISD::SELECT to vXi64.Craig Topper2018-10-031-3/+9
* [X86] Add CMOV_VK2/VK4 pseudos and remove lowering code that turned v2i1/v4i1...Craig Topper2018-10-031-10/+4
* [X86] Add CMOV pseudos for VR128X and VR256X register classes. Use them when ...Craig Topper2018-10-031-0/+4
* [X86] Don't break CMOV pseudo instructions down by type. Just by register class.Craig Topper2018-10-031-27/+14
* [X86] Correctly use SSE registers if no-x87 is selected.Nirav Dave2018-10-031-28/+36
* [X86] SimplifyDemandedVectorEltsForTargetNode - remove identity target shuffl...Simon Pilgrim2018-09-291-18/+18
* [X86][SSE] LowerScalarImmediateShift - remove 32-bit vXi64 special case handl...Simon Pilgrim2018-09-291-129/+65
* Fix signed/unsigned mismatch warning. NFCI.Simon Pilgrim2018-09-291-1/+1
* [X86] getTargetConstantBitsFromNode - add support for rearranging constant bi...Simon Pilgrim2018-09-291-0/+47
* [X86][SSE] LowerScalarImmediateShift - use getTargetConstantBitsFromNode to g...Simon Pilgrim2018-09-291-64/+74
* [X86] getTargetConstantBitsFromNode - fix self-move assertions from gcc build...Simon Pilgrim2018-09-291-2/+6
* [X86] getTargetConstantBitsFromNode - add support for peeking through ISD::EX...Simon Pilgrim2018-09-291-0/+15
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