summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/X86/X86ISelLowering.cpp
diff options
context:
space:
mode:
authorCraig Topper <craig.topper@intel.com>2018-10-05 18:13:36 +0000
committerCraig Topper <craig.topper@intel.com>2018-10-05 18:13:36 +0000
commit0ed892da707883908c8240087bed1e6286fe72aa (patch)
tree7ac0ccea4708936d402f809059616595ea09a041 /llvm/lib/Target/X86/X86ISelLowering.cpp
parent57b0da06881de3d4c37864fb074fe959e6b4a0bc (diff)
downloadbcm5719-llvm-0ed892da707883908c8240087bed1e6286fe72aa.tar.gz
bcm5719-llvm-0ed892da707883908c8240087bed1e6286fe72aa.zip
[X86] Don't promote i16 compares to i32 if the immediate will fit in 8 bits.
The comments in this code say we were trying to avoid 16-bit immediates, but if the immediate fits in 8-bits this isn't an issue. This avoids creating a zero extend that probably won't go away. The movmskb related changes are interesting. The movmskb instruction writes a 32-bit result, but fills the upper bits with 0. So the zero_extend we were previously emitting was free, but we turned a -1 immediate that would fit in 8-bits into a 32-bit immediate so it was still bad. llvm-svn: 343871
Diffstat (limited to 'llvm/lib/Target/X86/X86ISelLowering.cpp')
-rw-r--r--llvm/lib/Target/X86/X86ISelLowering.cpp7
1 files changed, 5 insertions, 2 deletions
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 91fa216c053..f63fd3e0463 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -18435,8 +18435,11 @@ SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
Op0.getValueType() == MVT::i32 || Op0.getValueType() == MVT::i64)) {
// Only promote the compare up to I32 if it is a 16 bit operation
// with an immediate. 16 bit immediates are to be avoided.
- if ((Op0.getValueType() == MVT::i16 &&
- (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1))) &&
+ if (Op0.getValueType() == MVT::i16 &&
+ ((isa<ConstantSDNode>(Op0) &&
+ !cast<ConstantSDNode>(Op0)->getAPIntValue().isSignedIntN(8)) ||
+ (isa<ConstantSDNode>(Op1) &&
+ !cast<ConstantSDNode>(Op1)->getAPIntValue().isSignedIntN(8))) &&
!DAG.getMachineFunction().getFunction().optForMinSize() &&
!Subtarget.isAtom()) {
unsigned ExtendOp =
OpenPOWER on IntegriCloud