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path: root/llvm/lib/Target/X86/X86ISelLowering.cpp
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* [AArch64] Improve code generation for logical instructions takingAkira Hatanaka2017-04-211-2/+2
* Revert r300932 and r300930.Akira Hatanaka2017-04-211-2/+2
* [AArch64] Improve code generation for logical instructions takingAkira Hatanaka2017-04-211-2/+2
* Revert "[AArch64] Improve code generation for logical instructions taking"Akira Hatanaka2017-04-201-2/+2
* [AArch64] Improve code generation for logical instructions takingAkira Hatanaka2017-04-201-2/+2
* [APInt] Rename getSignBit to getSignMaskCraig Topper2017-04-201-16/+16
* PR32710: Disable using PMADDWD for unsigned short.Dehao Chen2017-04-191-1/+1
* Add a getPointerOperandType() helper to LoadInst and StoreInst; NFCSanjoy Das2017-04-181-1/+1
* DAG: Make mayBeEmittedAsTailCall parameter constMatt Arsenault2017-04-181-2/+2
* [X86] Use for-range loop. NFCI.Simon Pilgrim2017-04-181-2/+2
* [APInt] Use lshrInPlace to replace lshr where possibleCraig Topper2017-04-181-5/+5
* [X86] Remove special handling for 16 bit for A asm constraints.Benjamin Kramer2017-04-161-6/+3
* Use correct registers for "A" inline asm constraintDimitry Andric2017-04-151-3/+13
* [X86] Create the correct ADC/SBB SDNode when lowering add.Davide Italiano2017-04-111-2/+4
* Module::getOrInsertFunction is using C-style vararg instead of variadic templ...Serge Guelton2017-04-111-1/+1
* Revert "Turn some C-style vararg into variadic templates"Diana Picus2017-04-111-1/+1
* Turn some C-style vararg into variadic templatesSerge Guelton2017-04-111-1/+1
* Use PMADDWD to expand reduction in a loopDehao Chen2017-04-071-0/+47
* [X86] Revert r299387 due to AVX legalization infinite loop.Michael Kuperstein2017-04-061-55/+1
* Revert "Turn some C-style vararg into variadic templates"Mehdi Amini2017-04-061-3/+4
* Turn some C-style vararg into variadic templatesMehdi Amini2017-04-061-4/+3
* [X86][SSE] Renamed combine to make it clear that it only handles the vector s...Simon Pilgrim2017-04-051-4/+5
* [X86] Relax assert in broadcast-of-subvector lowering.Ahmed Bougacha2017-04-051-2/+2
* [x86] remove dead select-of-constants transform; NFCISanjay Patel2017-04-041-12/+0
* Strip trailing whitespaceSimon Pilgrim2017-04-041-4/+4
* [X86] Add 64 bit pattern matching for PSADBWOren Ben Simhon2017-04-041-13/+41
* [X86][SSE]] Lower BUILD_VECTOR with repeated elts as BUILD_VECTOR + VECTOR_SH...Simon Pilgrim2017-04-031-1/+55
* x86 interrupt calling convention: re-align stack pointer on 64-bit if an erro...Amjad Aboud2017-04-031-2/+8
* [APInt] Move isMask and isShiftedMask out of APIntOps and into the APInt clas...Craig Topper2017-04-031-2/+2
* [X86][MMX] Improve support for folding fptosi from XMM to MMXSimon Pilgrim2017-04-021-0/+10
* [X86][MMX] Simplify tablegen patterns by always combining MOVDQ2Q from v2i64Simon Pilgrim2017-04-021-1/+2
* [X86][MMX] Added support for subvector extraction to MMX registerSimon Pilgrim2017-04-021-2/+4
* [AVX-512] Update lowering for gather/scatter prefetch intrinsics to match the...Craig Topper2017-03-311-3/+3
* [DAGCombiner] Add vector demanded elements support to ComputeNumSignBitsSimon Pilgrim2017-03-311-1/+2
* [DAGCombiner] Add vector demanded elements support to computeKnownBitsForTarg...Simon Pilgrim2017-03-311-0/+1
* Spelling mistakes in comments. NFCI.Simon Pilgrim2017-03-301-15/+15
* [X86IselLowering] Remove extraneous semicolon. NFCI.Davide Italiano2017-03-291-1/+1
* [X86] Tidied up comment - we don't custom lower add/sub i64 on i686 anymore. ...Simon Pilgrim2017-03-291-1/+2
* Spelling mistakes in comments. NFCI.Simon Pilgrim2017-03-291-5/+5
* [X86][AVX2] Prevent unary interleaving patterns from calling lowerVectorShuff...Simon Pilgrim2017-03-291-3/+4
* [X86][MMX] Match MMX fp_to_sint conversions from XMM registersSimon Pilgrim2017-03-281-4/+13
* [x86] use VPMOVMSK to replace memcmp libcalls for 32-byte equalitySanjay Patel2017-03-281-1/+5
* [X86][AVX2] Add support for combining v16i16 shuffles to VPBLENDWSimon Pilgrim2017-03-281-28/+47
* [X86][SSE] Refactored shuffle BLEND combining to make future 16i16 support ea...Simon Pilgrim2017-03-281-34/+33
* Fix signed/unsigned comparison warningSimon Pilgrim2017-03-281-2/+2
* [X86][SSE] Begin merging vector shuffle to BLEND for lowering and combining.Simon Pilgrim2017-03-281-70/+82
* [X86][SSE] Set second operand to undef instead of first operand in unary shuf...Simon Pilgrim2017-03-281-1/+2
* Strip trailing whitespaceSimon Pilgrim2017-03-281-1/+1
* [X86][AVX2] bugzilla bug 21281 Performance regression in vector interleave in...Gadi Haber2017-03-271-0/+33
* [X86][SSE] Add computeKnownBitsForTargetNode support for (V)PSLL/(V)PSRL inst...Simon Pilgrim2017-03-261-1/+26
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