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path: root/llvm/lib/Target/RISCV
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* [RISCV] Implement isLoadFromStackSlot and isStoreToStackSlotAlex Bradbury2018-04-262-0/+54
* [RISCV] Implement isZextFreeAlex Bradbury2018-04-262-0/+15
* [RISCV] Implement isTruncateFreeAlex Bradbury2018-04-262-0/+22
* [RISCV] Implement isLegalICmpImmediateAlex Bradbury2018-04-262-0/+5
* [RISCV] Implement isLegalAddImmediateAlex Bradbury2018-04-262-0/+5
* [RISCV] Implement isLegalAddressingMode for RISC-VAlex Bradbury2018-04-262-0/+30
* [RISCV] Allow call pseudoinstruction to be used to call a function name that ...Alex Bradbury2018-04-251-9/+12
* [RISCV] Expand function call to "call" pseudoinstructionShiva Chen2018-04-253-10/+18
* [RISCV] Support "call" pseudoinstruction in the MC layerShiva Chen2018-04-257-4/+110
* [RISCV] Introduce pattern for materialising immediates with 0 for lower 12 bitsAlex Bradbury2018-04-181-2/+3
* Revert "[RISCV] implement li pseudo instruction"Alex Bradbury2018-04-189-266/+49
* [RISCV] implement li pseudo instructionAlex Bradbury2018-04-179-49/+266
* [RISCV] Fix assert message operatorMandeep Singh Grang2018-04-161-1/+1
* [RISCV] Add c.mv rs1, rs2 pattern for addi rs1, rs2, 0Sameer AbuAsal2018-04-121-0/+2
* [RISCV] Change function alignment to 4 bytes, and 2 bytes for RVCShiva Chen2018-04-121-2/+3
* [RISCV] Codegen support for RV32D floating point comparison operationsAlex Bradbury2018-04-123-11/+37
* [RISCV] Codegen support for RV32D floating point conversion operationsAlex Bradbury2018-04-122-0/+15
* [RISCV] Add codegen support for RV32D floating point arithmetic operationsAlex Bradbury2018-04-122-1/+33
* [RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling ...Alex Bradbury2018-04-126-22/+327
* [NFC] fix trivial typos in comments and error messageHiroshi Inoue2018-04-091-1/+1
* [RISCV] Tablegen-driven Instruction Compression.Sameer AbuAsal2018-04-068-5/+332
* Sort targetgen calls in lib/Target/*/CMakeLists.Nico Weber2018-04-041-5/+5
* [IR][CodeGen] Remove dependency on EVT from IR/Function.cpp. Move EVT to Code...Craig Topper2018-03-291-1/+1
* [RISCV] Use init_array instead of ctors for RISCV target, by defaultMandeep Singh Grang2018-03-244-1/+47
* Fix layering by moving ValueTypes.h from CodeGen to IRDavid Blaikie2018-03-231-1/+1
* [RISCV] Codegen support for RV32F floating point comparison operationsAlex Bradbury2018-03-214-17/+70
* [RISCV] Add codegen for RV32F floating point load/storeAlex Bradbury2018-03-205-12/+51
* [RISCV] Add codegen for RV32F arithmetic and conversion operationsAlex Bradbury2018-03-202-5/+104
* [RISCV] Preserve stack space for outgoing arguments when the function contain...Shiva Chen2018-03-202-18/+38
* [RISCV] Peephole optimisation for load/store of global values or constant add...Alex Bradbury2018-03-191-0/+95
* [RISCV] Implement MC relaxations for compressed instructions.Sameer AbuAsal2018-03-021-7/+80
* [MachineOperand][Target] MachineOperand::isRenamable semantics changesGeoff Berry2018-02-231-0/+1
* [RISCV] Implement c.lui immediate operand constraintShiva Chen2018-02-223-10/+39
* [RISCV][NFC] Make logic in RISCVMCCodeEmitter::getImmOpValue more defensiveAlex Bradbury2018-02-221-5/+13
* [RISCV] Add support for %pcrel_lo.Ahmed Charles2018-02-067-12/+36
* [RISCV] Fix c.addi and c.addi16sp immediate constraints which should be non-zeroShiva Chen2018-02-022-9/+34
* [RISCV] Define getSetCCResultType for setting vector setCC typeShiva Chen2018-02-022-0/+10
* [SelectionDAGISel] Add a debug print before call to Select. Adjust where blan...Craig Topper2018-01-261-3/+0
* [RISCV] Encode RISCV specific ELF e_flags to RISCV Binary by RISCVTargetStreamerShiva Chen2018-01-266-0/+117
* [RISCV] Fixed setting predicates for compressed instructions.Ana Pazos2018-01-181-36/+38
* [RISCV] Codegen support for the standard RV32M instruction set extensionAlex Bradbury2018-01-182-8/+25
* [RISCV] Implement frame pointer eliminationAlex Bradbury2018-01-182-23/+24
* [RISCV] Allow RISCVAsmBackend::writeNopData to generate c.nop when supportedAlex Bradbury2018-01-171-8/+18
* [RISCV] Pass MCSubtargetInfo to print methods.Ana Pazos2018-01-123-9/+23
* [RISCV] Reserve an emergency spill slot for the register scavenger when neces...Alex Bradbury2018-01-112-0/+22
* [RISCV] Implement support for the BranchRelaxation passAlex Bradbury2018-01-105-9/+133
* [RISCV] Implement branch analysisAlex Bradbury2018-01-102-0/+182
* [RISCV] Add support for llvm.{frameaddress,returnaddress} intrinsicsAlex Bradbury2018-01-102-0/+59
* [RISCV] Add basic support for inline asm constraintsAlex Bradbury2018-01-104-0/+96
* [RISCV] Support stack frames and offsets up to 32-bitsAlex Bradbury2018-01-105-11/+79
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