summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/RISCV
diff options
context:
space:
mode:
authorAna Pazos <apazos@codeaurora.org>2018-01-12 02:27:00 +0000
committerAna Pazos <apazos@codeaurora.org>2018-01-12 02:27:00 +0000
commite3d248361eecf4a6d8d394821a2407f292f9bf98 (patch)
treea7197b80f27990099ec8f412e63770a05b51df96 /llvm/lib/Target/RISCV
parentd7f96d0b9197293115fccae806e889ff35512191 (diff)
downloadbcm5719-llvm-e3d248361eecf4a6d8d394821a2407f292f9bf98.tar.gz
bcm5719-llvm-e3d248361eecf4a6d8d394821a2407f292f9bf98.zip
[RISCV] Pass MCSubtargetInfo to print methods.
Summary: This change allows checking for ISA extensions in print methods. Reviewers: asb, niosHD Reviewed By: asb, niosHD Subscribers: llvm-commits, niosHD, asb, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal Differential Revision: https://reviews.llvm.org/D41503 llvm-svn: 322345
Diffstat (limited to 'llvm/lib/Target/RISCV')
-rw-r--r--llvm/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp8
-rw-r--r--llvm/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.h19
-rw-r--r--llvm/lib/Target/RISCV/RISCV.td5
3 files changed, 23 insertions, 9 deletions
diff --git a/llvm/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp
index ff56fc5d90f..f1fa2ecbcb2 100644
--- a/llvm/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp
+++ b/llvm/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp
@@ -17,6 +17,7 @@
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/MC/MCSymbol.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ErrorHandling.h"
@@ -37,8 +38,8 @@ NoAliases("riscv-no-aliases",
void RISCVInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
StringRef Annot, const MCSubtargetInfo &STI) {
- if (NoAliases || !printAliasInstr(MI, O))
- printInstruction(MI, O);
+ if (NoAliases || !printAliasInstr(MI, STI, O))
+ printInstruction(MI, STI, O);
printAnnotation(O, Annot);
}
@@ -47,6 +48,7 @@ void RISCVInstPrinter::printRegName(raw_ostream &O, unsigned RegNo) const {
}
void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
+ const MCSubtargetInfo &STI,
raw_ostream &O, const char *Modifier) {
assert((Modifier == 0 || Modifier[0] == 0) && "No modifiers supported");
const MCOperand &MO = MI->getOperand(OpNo);
@@ -66,6 +68,7 @@ void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
}
void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo,
+ const MCSubtargetInfo &STI,
raw_ostream &O) {
unsigned FenceArg = MI->getOperand(OpNo).getImm();
if ((FenceArg & RISCVFenceField::I) != 0)
@@ -79,6 +82,7 @@ void RISCVInstPrinter::printFenceArg(const MCInst *MI, unsigned OpNo,
}
void RISCVInstPrinter::printFRMArg(const MCInst *MI, unsigned OpNo,
+ const MCSubtargetInfo &STI,
raw_ostream &O) {
auto FRMArg =
static_cast<RISCVFPRndMode::RoundingMode>(MI->getOperand(OpNo).getImm());
diff --git a/llvm/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.h b/llvm/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.h
index 58f3f841015..241be8daf11 100644
--- a/llvm/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.h
+++ b/llvm/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.h
@@ -30,16 +30,21 @@ public:
const MCSubtargetInfo &STI) override;
void printRegName(raw_ostream &O, unsigned RegNo) const override;
- void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O,
- const char *Modifier = nullptr);
- void printFenceArg(const MCInst *MI, unsigned OpNo, raw_ostream &O);
- void printFRMArg(const MCInst *MI, unsigned OpNo, raw_ostream &O);
+ void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
+ raw_ostream &O, const char *Modifier = nullptr);
+ void printFenceArg(const MCInst *MI, unsigned OpNo,
+ const MCSubtargetInfo &STI, raw_ostream &O);
+ void printFRMArg(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
+ raw_ostream &O);
// Autogenerated by tblgen.
- void printInstruction(const MCInst *MI, raw_ostream &O);
- bool printAliasInstr(const MCInst *MI, raw_ostream &O);
+ void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
+ raw_ostream &O);
+ bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
+ raw_ostream &O);
void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
- unsigned PrintMethodIdx, raw_ostream &O);
+ unsigned PrintMethodIdx,
+ const MCSubtargetInfo &STI, raw_ostream &O);
static const char *getRegisterName(unsigned RegNo,
unsigned AltIdx = RISCV::ABIRegAltName);
};
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index c74d560b2e0..4caaaa43c10 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -84,7 +84,12 @@ def RISCVAsmParser : AsmParser {
let AllowDuplicateRegisterNames = 1;
}
+def RISCVAsmWriter : AsmWriter {
+ int PassSubtarget = 1;
+}
+
def RISCV : Target {
let InstructionSet = RISCVInstrInfo;
let AssemblyParsers = [RISCVAsmParser];
+ let AssemblyWriters = [RISCVAsmWriter];
}
OpenPOWER on IntegriCloud