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path: root/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
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* [RISCV] Correct the CallPreservedMask for the function call in an interrupt h...Shiva Chen2020-02-201-7/+0
* [RISCV] Handle variable sized objects with the stack need to be realignedShiva Chen2019-11-161-1/+5
* [RISCV] Remove RA from reserved register to use as callee saved registerShiva Chen2019-10-291-1/+0
* [RISCV] Add support for -ffixed-xX flagsSimon Cook2019-10-221-0/+11
* [RISCV] Rename FPRs and use Register arithmeticLuis Marques2019-09-271-0/+9
* [RISCV] Support stack offset exceed 32-bit for RV64Shiva Chen2019-09-131-1/+1
* Revert "[RISCV] Support stack offset exceed 32-bit for RV64"Shiva Chen2019-09-131-1/+1
* [RISCV] Support stack offset exceed 32-bit for RV64Shiva Chen2019-09-131-1/+1
* [risc-v] Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders2019-08-121-1/+1
* CodeGen: Introduce a class for registersMatt Arsenault2019-06-241-1/+1
* [RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float...Alex Bradbury2019-03-301-2/+28
* [RISCV] Fix rL356123Alex Bradbury2019-03-141-2/+2
* [RISCV][NFC] Rename callee saved regs 'CSR' to CSR_ILP32_LP64 and minor RISCV...Alex Bradbury2019-03-141-6/+8
* [RISCV] Only mark fp as reserved if the function has a dedicated frame pointerAlex Bradbury2019-03-131-1/+3
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [RISCV] Add support for _interrupt attributeAna Pazos2018-07-261-1/+15
* [RISCV] Set isReMaterializable on ADDI and LUI instructionsAlex Bradbury2018-05-171-0/+4
* [RISCV] Implement frame pointer eliminationAlex Bradbury2018-01-181-4/+2
* [RISCV] Support stack frames and offsets up to 32-bitsAlex Bradbury2018-01-101-4/+23
* [RISCV] Support lowering FrameIndexAlex Bradbury2017-12-111-8/+6
* [RISCV] Silence an unused variable warning in release builds [NFC]Mandeep Singh Grang2017-11-101-1/+0
* [RISCV] Initial support for function callsAlex Bradbury2017-11-081-0/+6
* [RISCV] Codegen for conditional branchesAlex Bradbury2017-11-081-1/+30
* Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie2017-11-081-2/+2
* Move TargetFrameLowering.h to CodeGen where it's implementedDavid Blaikie2017-11-031-1/+1
* [RISCV] Initial codegen support for ALU operationsAlex Bradbury2017-10-191-0/+61
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