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authorAlex Bradbury <asb@lowrisc.org>2017-12-11 11:53:54 +0000
committerAlex Bradbury <asb@lowrisc.org>2017-12-11 11:53:54 +0000
commit660bcceccf85bfc2bbac4f28b87e94c1f3e82184 (patch)
treef912cc41c2b4669b0c611f253189434ef857902d /llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
parent775bb7437932ea6141c33ab63074640fb541997e (diff)
downloadbcm5719-llvm-660bcceccf85bfc2bbac4f28b87e94c1f3e82184.tar.gz
bcm5719-llvm-660bcceccf85bfc2bbac4f28b87e94c1f3e82184.zip
[RISCV] Support lowering FrameIndex
Introduces the AddrFI "addressing mode", which is necessary simply because it's not possible to write a pattern that directly matches a frameindex. Ensure callee-saved registers are accessed relative to the stackpointer. This is necessary as callee-saved register spills are performed before the frame pointer is set. Move HexagonDAGToDAGISel::isOrEquivalentToAdd to SelectionDAGISel, so we can make use of it in the RISC-V backend. Differential Revision: https://reviews.llvm.org/D39848 llvm-svn: 320353
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp')
-rw-r--r--llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp14
1 files changed, 6 insertions, 8 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index 75b277531ce..5776a92cab9 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -57,22 +57,20 @@ const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const {
void RISCVRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, unsigned FIOperandNum,
RegScavenger *RS) const {
- // TODO: this implementation is a temporary placeholder which does just
- // enough to allow other aspects of code generation to be tested
-
assert(SPAdj == 0 && "Unexpected non-zero SPAdj value");
MachineInstr &MI = *II;
MachineFunction &MF = *MI.getParent()->getParent();
- const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering();
DebugLoc DL = MI.getDebugLoc();
- unsigned FrameReg = getFrameRegister(MF);
int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
- int Offset = TFI->getFrameIndexReference(MF, FrameIndex, FrameReg);
- Offset += MI.getOperand(FIOperandNum + 1).getImm();
+ unsigned FrameReg;
+ int Offset =
+ getFrameLowering(MF)->getFrameIndexReference(MF, FrameIndex, FrameReg) +
+ MI.getOperand(FIOperandNum + 1).getImm();
- assert(TFI->hasFP(MF) && "eliminateFrameIndex currently requires hasFP");
+ assert(MF.getSubtarget().getFrameLowering()->hasFP(MF) &&
+ "eliminateFrameIndex currently requires hasFP");
// Offsets must be directly encoded in a 12-bit immediate field
if (!isInt<12>(Offset)) {
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