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| author | Alex Bradbury <asb@lowrisc.org> | 2019-03-14 08:28:48 +0000 |
|---|---|---|
| committer | Alex Bradbury <asb@lowrisc.org> | 2019-03-14 08:28:48 +0000 |
| commit | 8dbc6398e17a957db0cfc4fc95d2d2d1517a3ed0 (patch) | |
| tree | f50270fa31472f9dcfbea9a57f5c39197cb6dd29 /llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | |
| parent | d08ed38e084b84db952b3c21fa759a81397675fb (diff) | |
| download | bcm5719-llvm-8dbc6398e17a957db0cfc4fc95d2d2d1517a3ed0.tar.gz bcm5719-llvm-8dbc6398e17a957db0cfc4fc95d2d2d1517a3ed0.zip | |
[RISCV][NFC] Rename callee saved regs 'CSR' to CSR_ILP32_LP64 and minor RISCVRegisterInfo refactoring
The CSR renaming further prepares the way for an upcoming patch adding support for more
RISC-V ABIs.
Modify RISCVRegisterInfo::getCalleeSavedRegs and
RISCVRegisterInfo::getReservedRegs to do MF->getSubtarget<RISCVSubtarget>()
once rather than multiple times.
llvm-svn: 356123
Diffstat (limited to 'llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp index 38af3827e4c..0beb166ec00 100644 --- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp @@ -32,14 +32,15 @@ RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode) const MCPhysReg * RISCVRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { + auto &Subtarget = MF->getSubtarget<RISCVSubtarget>(); if (MF->getFunction().hasFnAttribute("interrupt")) { - if (MF->getSubtarget<RISCVSubtarget>().hasStdExtD()) + if (Subtarget.hasStdExtD()) return CSR_XLEN_F64_Interrupt_SaveList; - if (MF->getSubtarget<RISCVSubtarget>().hasStdExtF()) + if (Subtarget..hasStdExtF()) return CSR_XLEN_F32_Interrupt_SaveList; return CSR_Interrupt_SaveList; } - return CSR_SaveList; + return CSR_ILP32_LP64_SaveList; } BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const { @@ -118,12 +119,13 @@ unsigned RISCVRegisterInfo::getFrameRegister(const MachineFunction &MF) const { const uint32_t * RISCVRegisterInfo::getCallPreservedMask(const MachineFunction & MF, CallingConv::ID /*CC*/) const { + auto &Subtarget = MF->getSubtarget<RISCVSubtarget>(); if (MF.getFunction().hasFnAttribute("interrupt")) { - if (MF.getSubtarget<RISCVSubtarget>().hasStdExtD()) + if (Subtarget.hasStdExtD()) return CSR_XLEN_F64_Interrupt_RegMask; - if (MF.getSubtarget<RISCVSubtarget>().hasStdExtF()) + if (Subtarget.hasStdExtF()) return CSR_XLEN_F32_Interrupt_RegMask; return CSR_Interrupt_RegMask; } - return CSR_RegMask; + return CSR_ILP32_LP64_RegMask; } |

