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path: root/llvm/lib/Target/RISCV/RISCVInstrInfo.h
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* [RISCV] Enable the machine outliner for RISC-Vlewis-revill2019-12-191-0/+29
* [RISCV] Machine Operand Flag SerializationSam Elliott2019-12-091-0/+7
* Use MCRegister in copyPhysRegMatt Arsenault2019-11-111-1/+1
* [RISCV] Add InstrInfo areMemAccessesTriviallyDisjoint hookLuís Marques2019-11-051-0/+8
* [RISCV] Add MachineInstr immediate verificationLuis Marques2019-10-161-1/+9
* [RISCV] Support stack offset exceed 32-bit for RV64Shiva Chen2019-09-131-4/+4
* Revert "[RISCV] Support stack offset exceed 32-bit for RV64"Shiva Chen2019-09-131-4/+4
* [RISCV] Support stack offset exceed 32-bit for RV64Shiva Chen2019-09-131-4/+4
* [RISCV] Convert registers from unsigned to RegisterLuis Marques2019-08-161-1/+1
* Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUIAna Pazos2019-01-251-0/+2
* Revert "[RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI"Ana Pazos2019-01-241-2/+0
* [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUIAna Pazos2019-01-241-0/+2
* Update the file headers across all of the LLVM projects in the monorepoChandler Carruth2019-01-191-4/+3
* [RISCV] Implement isLoadFromStackSlot and isStoreToStackSlotAlex Bradbury2018-04-261-0/+5
* [RISCV] Implement support for the BranchRelaxation passAlex Bradbury2018-01-101-0/+12
* [RISCV] Implement branch analysisAlex Bradbury2018-01-101-0/+16
* [RISCV] Support stack frames and offsets up to 32-bitsAlex Bradbury2018-01-101-0/+5
* [RISCV] Codegen for conditional branchesAlex Bradbury2017-11-081-1/+11
* [RISCV] Codegen support for memory operationsAlex Bradbury2017-11-081-0/+4
* Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie2017-11-081-1/+1
* [RISCV] Initial codegen support for ALU operationsAlex Bradbury2017-10-191-0/+32
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