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path: root/llvm/lib/Target/RISCV/RISCVISelLowering.h
Commit message (Expand)AuthorAgeFilesLines
* [RISCV] Remove unused functionRoger Ferrer Ibanez2018-08-171-1/+0
* [RISCV] Add support for _interrupt attributeAna Pazos2018-07-261-0/+3
* [RISCV] Add codegen support for atomic load/stores with RV32AAlex Bradbury2018-06-131-0/+8
* [RISCV] Lower the tail pseudoinstructionMandeep Singh Grang2018-05-231-1/+6
* [RISCV] Implement isZextFreeAlex Bradbury2018-04-261-0/+1
* [RISCV] Implement isTruncateFreeAlex Bradbury2018-04-261-0/+2
* [RISCV] Implement isLegalICmpImmediateAlex Bradbury2018-04-261-0/+1
* [RISCV] Implement isLegalAddImmediateAlex Bradbury2018-04-261-0/+1
* [RISCV] Implement isLegalAddressingMode for RISC-VAlex Bradbury2018-04-261-0/+4
* [RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling ...Alex Bradbury2018-04-121-1/+3
* [RISCV] Add codegen for RV32F floating point load/storeAlex Bradbury2018-03-201-0/+1
* [RISCV] Define getSetCCResultType for setting vector setCC typeShiva Chen2018-02-021-0/+3
* [RISCV] Add support for llvm.{frameaddress,returnaddress} intrinsicsAlex Bradbury2018-01-101-0/+2
* [RISCV] Add basic support for inline asm constraintsAlex Bradbury2018-01-101-0/+4
* [RISCV] Support for varargsAlex Bradbury2018-01-101-1/+2
* [RISCV] Add custom CC_RISCV calling convention and improved call supportAlex Bradbury2017-12-111-0/+10
* [RISCV] Support and tests for a variety of additional LLVM IR constructsAlex Bradbury2017-11-211-0/+2
* [RISCV] Implement lowering of ISD::SELECTAlex Bradbury2017-11-211-1/+7
* Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie2017-11-171-1/+1
* [RISCV] Initial support for function callsAlex Bradbury2017-11-081-1/+4
* [RISCV] Codegen support for memory operations on global addressesAlex Bradbury2017-11-081-0/+1
* [RISCV] Initial codegen support for ALU operationsAlex Bradbury2017-10-191-0/+62
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