summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
Commit message (Expand)AuthorAgeFilesLines
...
* [RISCV][MC] Improve parsing of jal/j operandsAlex Bradbury2018-09-201-2/+20
* [RISCV][MC] Use a custom ParserMethod for the bare_symbol operand typeAlex Bradbury2018-09-181-30/+35
* [RISCV][MC] Reject bare symbols for the simm12 operand typeAlex Bradbury2018-09-181-3/+5
* [RISCV][MC] Tighten up checking of sybol operands to lui and auipcAlex Bradbury2018-09-181-9/+32
* [RISCV][MC] Reject bare symbols for the simm6 and simm6nonzero operand typesAna Pazos2018-09-131-14/+4
* [RISCV] Fixed SmallVector.h Assertion `idx < size()'Ana Pazos2018-08-301-1/+17
* [RISCV] Fixed Assertion`Kind == Immediate && "Invalid type access!"' failed.Ana Pazos2018-08-241-0/+18
* [RISCV] Fix incorrect use of MCInstBuilderRoger Ferrer Ibanez2018-08-141-8/+6
* [RISCV] Add "lla" pseudo-instruction to assemblerRoger Ferrer Ibanez2018-08-091-3/+64
* [RISCV] AsmParser support for the li pseudo instructionAlex Bradbury2018-06-071-10/+147
* [RISCV] Implement MC layer support for the tail pseudoinstructionMandeep Singh Grang2018-05-171-1/+2
* [RISCV] Add support for .half, .hword, .word, .dword directivesAlex Bradbury2018-05-171-0/+4
* [RISCV] Support .option rvc and norvc assembler directivesAlex Bradbury2018-05-111-1/+77
* [RISCV] Allow call pseudoinstruction to be used to call a function name that ...Alex Bradbury2018-04-251-9/+12
* [RISCV] Support "call" pseudoinstruction in the MC layerShiva Chen2018-04-251-0/+14
* Revert "[RISCV] implement li pseudo instruction"Alex Bradbury2018-04-181-59/+10
* [RISCV] implement li pseudo instructionAlex Bradbury2018-04-171-10/+59
* [NFC] fix trivial typos in comments and error messageHiroshi Inoue2018-04-091-1/+1
* [RISCV] Tablegen-driven Instruction Compression.Sameer AbuAsal2018-04-061-2/+10
* [RISCV] Implement c.lui immediate operand constraintShiva Chen2018-02-221-5/+8
* [RISCV] Add support for %pcrel_lo.Ahmed Charles2018-02-061-2/+3
* [RISCV] Fix c.addi and c.addi16sp immediate constraints which should be non-zeroShiva Chen2018-02-021-4/+21
* [RISCV] Change shift amount operand of RVC shift instructions to uimmlog2xlen...Alex Bradbury2017-12-151-2/+16
* [RISCV][NFC] Put isSImm6 and simm6 td definition in correct sorted positionAlex Bradbury2017-12-131-16/+16
* [RISCV] MC layer support for the remaining RVC instructionsAlex Bradbury2017-12-131-2/+67
* [RISCV] MC layer support for the jump/branch instructions of the RVC extensionAlex Bradbury2017-12-071-0/+12
* [RISCV] MC layer support for load/store instructions of the C (compressed) ex...Alex Bradbury2017-12-071-0/+48
* [RISCV] MC layer support for the standard RV64I instructionsAlex Bradbury2017-12-071-11/+35
* [RISCV] MC layer support for the standard RV32D instruction set extensionAlex Bradbury2017-12-071-0/+64
* [RISCV] MC layer support for the standard RV32F instruction set extensionAlex Bradbury2017-12-071-0/+36
* [RISCV] MC layer support for the standard RV32A instruction set extensionAlex Bradbury2017-11-091-6/+31
* [RISCV] RISCVAsmParser: early exit if RISCVOperand isn't immediate as expectedAlex Bradbury2017-10-191-0/+10
* [RISCV][NFC] Drop unused parameter from createImm helper in RISCVAsmParserAlex Bradbury2017-10-191-4/+3
* [Asm] Add debug tracing in table-generated assembly matcherOliver Stannard2017-10-111-1/+2
* [RISCV] Add common fixups and relocationsAlex Bradbury2017-09-281-20/+162
* [RISCV] Add support for all RV32I instructionsAlex Bradbury2017-09-171-11/+145
* [RISCV][NFC] Fix sorting of includes in lib/Target/RISCVAlex Bradbury2017-09-061-5/+5
* [RISCV] Fix warning about unused getSubtargetFeatureName()Alex Bradbury2017-08-081-1/+0
* [RISCV] Add basic RISCVAsmParser (missing files)Alex Bradbury2017-08-081-0/+373
OpenPOWER on IntegriCloud