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* Use MCRegister in copyPhysRegMatt Arsenault2019-11-112-3/+3
* [RISCV] Fix CFA when doing split sp adjustment with fpLuís Marques2019-11-101-15/+25
* [RISCV][NFC] Add CFI-related testsLuís Marques2019-11-101-0/+2
* [RISCV] Fix evaluation of %pcrel_loRoger Ferrer Ibanez2019-11-081-3/+7
* [RISCV] Add InstrInfo areMemAccessesTriviallyDisjoint hookLuís Marques2019-11-052-0/+63
* [RISCV] Implement the TargetLowering::getRegisterByName hookLuís Marques2019-11-042-0/+26
* [RISCV] Remove RA from reserved register to use as callee saved registerShiva Chen2019-10-291-1/+0
* [RISCV] Lower llvm.trap and llvm.debugtrapSam Elliott2019-10-282-0/+13
* [RISCV] Add support for half-precision floatsLuís Marques2019-10-251-1/+6
* [Mips] Use appropriate private label prefix based on Mips ABIMirko Brkusanin2019-10-231-1/+2
* [RISCV] Add support for -ffixed-xX flagsSimon Cook2019-10-228-0/+79
* [Alignment][NFC] Use Align for TargetFrameLowering/SubtargetGuillaume Chatelet2019-10-171-1/+1
* [RISCV] Add MachineInstr immediate verificationLuis Marques2019-10-166-4/+101
* [RISCV] Support fast calling conventionShiva Chen2019-10-151-2/+67
* [RISCV] Added missing ImmLeaf predicatesAna Pazos2019-10-041-2/+4
* [RISCV] Split SP adjustment to reduce the offset of callee saved register spi...Shiva Chen2019-10-042-1/+90
* [RISCV] Add obsolete aliases of fscsr, frcsr (fssr, frsr)Edward Jones2019-10-031-0/+6
* [RISCV] Rename FPRs and use Register arithmeticLuis Marques2019-09-276-199/+136
* [Alignment][NFC] Remove unneeded llvm:: scoping on Align typesGuillaume Chatelet2019-09-271-1/+1
* [RISCV] Fix static analysis issuesLuis Marques2019-09-203-5/+4
* Reapply r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"Matt Arsenault2019-09-191-4/+4
* Revert r372285 "GlobalISel: Don't materialize immarg arguments to intrinsics"Hans Wennborg2019-09-191-4/+4
* GlobalISel: Don't materialize immarg arguments to intrinsicsMatt Arsenault2019-09-191-4/+4
* [RISCV] Unbreak the buildBenjamin Kramer2019-09-171-4/+4
* [RISCV][NFC] Use NoRegister instead of 0 literalLuis Marques2019-09-171-4/+4
* [RISCV] Switch to the Machine SchedulerLuis Marques2019-09-171-0/+1
* Revert Patch from PhabricatorLuis Marques2019-09-171-1/+0
* Patch from PhabricatorLuis Marques2019-09-171-0/+1
* [RISCV] Support stack offset exceed 32-bit for RV64Shiva Chen2019-09-134-27/+45
* Revert "[RISCV] Support stack offset exceed 32-bit for RV64"Shiva Chen2019-09-134-44/+27
* [RISCV] Support stack offset exceed 32-bit for RV64Shiva Chen2019-09-134-27/+44
* [RISCV] Support llvm-objdump -M no-aliases and -M numericSam Elliott2019-09-102-0/+20
* [RISCV] Add Option for Printing Architectural Register NamesSam Elliott2019-09-102-2/+13
* [Alignment][NFC] Use Align with TargetLowering::setPrefFunctionAlignmentGuillaume Chatelet2019-09-061-2/+2
* [Alignment][NFC] Use Align with TargetLowering::setMinFunctionAlignmentGuillaume Chatelet2019-09-061-3/+3
* [LLVM][Alignment] Make functions using log of alignment explicitGuillaume Chatelet2019-09-051-2/+2
* [RISCV] Enable tail call opt for variadic functionJim Lin2019-09-041-5/+0
* [RISCV] Avoid generating AssertZext for LP64 ABI when lowering floating LibCallShiva Chen2019-08-282-0/+12
* [RISCV] Implement RISCVRegisterInfo::getPointerRegClassLuis Marques2019-08-271-0/+6
* Do a sweep of symbol internalization. NFC.Benjamin Kramer2019-08-232-3/+3
* [MC] Minor cleanup to MCFixup::Kind handling. NFC.Sam Clegg2019-08-232-6/+5
* [RISCV] Remove fix introduced by r369573, superseded by r369580Luis Marques2019-08-211-3/+0
* [RISCV] Fix use of side-effects in asserts in decoder functionsLuis Marques2019-08-211-6/+9
* Fix -Werror=unused-variable error after r369528.Richard Smith2019-08-211-0/+3
* [RISCV] Add support for RVC HINT instructionsLuis Marques2019-08-217-3/+212
* [RISCV GlobalISel] Adding initial GlobalISel infrastructureDaniel Sanders2019-08-2015-2/+412
* [RISCV] Implement getExprForFDESymbol to ensure RISCV_32_PCREL is used for th...Alex Bradbury2019-08-205-0/+30
* [RISCV] Don't force absolute FK_Data_X fixups to relocsAlex Bradbury2019-08-191-0/+7
* [RISCV] Convert registers from unsigned to RegisterLuis Marques2019-08-1611-78/+82
* [RISCV] Allow parsing of bare symbols with offsetsLewis Revill2019-08-161-0/+18
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