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| author | Tom Stellard <thomas.stellard@amd.com> | 2015-05-25 16:15:50 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2015-05-25 16:15:50 +0000 |
| commit | c70cf90d09b79271ea898d5998690ef0f370acf7 (patch) | |
| tree | 38052fcf4e170bb4ccf584b6643a3ef39d56fba0 /llvm/lib/Target/R600 | |
| parent | 5944ee2179c862a0793ceeeab68e1361f77f6f80 (diff) | |
| download | bcm5719-llvm-c70cf90d09b79271ea898d5998690ef0f370acf7.tar.gz bcm5719-llvm-c70cf90d09b79271ea898d5998690ef0f370acf7.zip | |
R600/SI: Use NAME rather than opName as the key to the MCOpcode tables
This lets us drop a parameter the opName parameter to the VINTRP
multiclass and makes it possible to create multiple VINTRP defs
with the same asm mnemonic.
llvm-svn: 238146
Diffstat (limited to 'llvm/lib/Target/R600')
| -rw-r--r-- | llvm/lib/Target/R600/SIInstrInfo.td | 8 | ||||
| -rw-r--r-- | llvm/lib/Target/R600/SIInstructions.td | 6 |
2 files changed, 7 insertions, 7 deletions
diff --git a/llvm/lib/Target/R600/SIInstrInfo.td b/llvm/lib/Target/R600/SIInstrInfo.td index c154bb660ab..12e9d4f24bb 100644 --- a/llvm/lib/Target/R600/SIInstrInfo.td +++ b/llvm/lib/Target/R600/SIInstrInfo.td @@ -1770,16 +1770,16 @@ class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins, VINTRPe_vi <op>, SIMCInstr<opName, SISubtarget.VI>; -multiclass VINTRP_m <bits <2> op, string opName, dag outs, dag ins, string asm, +multiclass VINTRP_m <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern = [], string disableEncoding = "", string constraints = ""> { let DisableEncoding = disableEncoding, Constraints = constraints in { - def "" : VINTRP_Pseudo <opName, outs, ins, pattern>; + def "" : VINTRP_Pseudo <NAME, outs, ins, pattern>; - def _si : VINTRP_Real_si <op, opName, outs, ins, asm>; + def _si : VINTRP_Real_si <op, NAME, outs, ins, asm>; - def _vi : VINTRP_Real_vi <op, opName, outs, ins, asm>; + def _vi : VINTRP_Real_vi <op, NAME, outs, ins, asm>; } } diff --git a/llvm/lib/Target/R600/SIInstructions.td b/llvm/lib/Target/R600/SIInstructions.td index b43c802d034..875f9c96bf0 100644 --- a/llvm/lib/Target/R600/SIInstructions.td +++ b/llvm/lib/Target/R600/SIInstructions.td @@ -1437,7 +1437,7 @@ let Uses = [M0] in { // FIXME: Specify SchedRW for VINTRP insturctions. defm V_INTERP_P1_F32 : VINTRP_m < - 0x00000000, "v_interp_p1_f32", + 0x00000000, (outs VGPR_32:$dst), (ins VGPR_32:$i, i32imm:$attr_chan, i32imm:$attr), "v_interp_p1_f32 $dst, $i, $attr_chan, $attr, [m0]", @@ -1445,7 +1445,7 @@ defm V_INTERP_P1_F32 : VINTRP_m < (i32 imm:$attr)))]>; defm V_INTERP_P2_F32 : VINTRP_m < - 0x00000001, "v_interp_p2_f32", + 0x00000001, (outs VGPR_32:$dst), (ins VGPR_32:$src0, VGPR_32:$j, i32imm:$attr_chan, i32imm:$attr), "v_interp_p2_f32 $dst, [$src0], $j, $attr_chan, $attr, [m0]", @@ -1455,7 +1455,7 @@ defm V_INTERP_P2_F32 : VINTRP_m < "$src0 = $dst">; defm V_INTERP_MOV_F32 : VINTRP_m < - 0x00000002, "v_interp_mov_f32", + 0x00000002, (outs VGPR_32:$dst), (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr), "v_interp_mov_f32 $dst, $src0, $attr_chan, $attr, [m0]", |
