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authorDaniel Sanders <daniel.sanders@imgtec.com>2015-06-10 10:35:34 +0000
committerDaniel Sanders <daniel.sanders@imgtec.com>2015-06-10 10:35:34 +0000
commit418caf5002effdbfe735a82c91b409fe30d4d280 (patch)
treef03baf4340cd07d12d21a8617f4446e0160cbfd5 /llvm/lib/Target/R600
parent056c45a4a1ca505b5458a42516bd0e20a4f039c5 (diff)
downloadbcm5719-llvm-418caf5002effdbfe735a82c91b409fe30d4d280.tar.gz
bcm5719-llvm-418caf5002effdbfe735a82c91b409fe30d4d280.zip
Replace string GNU Triples with llvm::Triple in MCAsmBackend subclasses and create*AsmBackend(). NFC.
Summary: This continues the patch series to eliminate StringRef forms of GNU triples from the internals of LLVM that began in r239036. Reviewers: echristo, rafael Reviewed By: rafael Subscribers: rafael, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D10243 llvm-svn: 239464
Diffstat (limited to 'llvm/lib/Target/R600')
-rw-r--r--llvm/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp3
-rw-r--r--llvm/lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.h3
2 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp b/llvm/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp
index 3713223697e..8bed2deef4c 100644
--- a/llvm/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp
+++ b/llvm/lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp
@@ -139,7 +139,6 @@ public:
MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T,
const MCRegisterInfo &MRI,
- StringRef TT,
- StringRef CPU) {
+ const Triple &TT, StringRef CPU) {
return new ELFAMDGPUAsmBackend(T);
}
diff --git a/llvm/lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.h b/llvm/lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.h
index 9a7548e9fbf..92e29dc7037 100644
--- a/llvm/lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.h
+++ b/llvm/lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.h
@@ -28,6 +28,7 @@ class MCObjectWriter;
class MCRegisterInfo;
class MCSubtargetInfo;
class Target;
+class Triple;
class raw_pwrite_stream;
class raw_ostream;
@@ -43,7 +44,7 @@ MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII,
MCContext &Ctx);
MCAsmBackend *createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI,
- StringRef TT, StringRef CPU);
+ const Triple &TT, StringRef CPU);
MCObjectWriter *createAMDGPUELFObjectWriter(raw_pwrite_stream &OS);
} // End llvm namespace
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