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* R600/SI: Handle INSERT_SUBREG in SIFixSGPRCopiesTom Stellard2014-04-072-0/+12
| | | | llvm-svn: 205732
* R600: Match 24-bit arithmetic patterns in a Target DAGCombineTom Stellard2014-04-0711-58/+115
| | | | | | | | | | | | | | | | | Moving these patterns from TableGen files to PerformDAGCombine() should allow us to generate better code by eliminating unnecessary shifts and extensions earlier. This also fixes a bug where the MAD pattern was calling SimplifyDemandedBits with a 24-bit mask on the first operand even when the full pattern wasn't being matched. This occasionally resulted in some instructions being incorrectly deleted from the program. v2: - Fix bug with 64-bit mul llvm-svn: 205731
* R600: Replace dyn_cast + assert with castTom Stellard2014-04-071-2/+1
| | | | llvm-svn: 205730
* Use std::swapMatt Arsenault2014-04-071-3/+1
| | | | llvm-svn: 205723
* Use .data() instead of &x[0]Matt Arsenault2014-04-072-18/+21
| | | | llvm-svn: 205722
* MachineInstr: introduce explicit_operands and implicit_operands rangesDavid Blaikie2014-04-051-3/+1
| | | | | | | Makes iteration over implicit and explicit machine operands more explicit (har har). Insipired by code review discussion for r205565. llvm-svn: 205680
* Fix tabsMatt Arsenault2014-04-041-5/+5
| | | | llvm-svn: 205648
* Make consistent use of MCPhysReg instead of uint16_t throughout the tree.Craig Topper2014-04-042-5/+5
| | | | llvm-svn: 205610
* R600: Correct opcode for BFE_INTTom Stellard2014-04-031-1/+1
| | | | | | | | | | | Acording to AMD documentation, the correct opcode for BFE_INT is 0x5, not 0x4 Fixes Arithm/Absdiff.Mat/3 OpenCV test Patch by: Bruno Jiménez llvm-svn: 205562
* R600/SI: Lower 64-bit immediates using REG_SEQUENCETom Stellard2014-04-034-19/+43
| | | | llvm-svn: 205561
* R600/SI: Remove leftover pattern splitting 64-bit ors.Matt Arsenault2014-03-311-8/+0
| | | | | | | It's now matched to the scalar 64-bit or and split later if necessary.' llvm-svn: 205252
* Change shouldSplitVectorElementType to better match the description.Matt Arsenault2014-03-312-3/+3
| | | | | | Pass the entire vector type, and not just the element. llvm-svn: 205247
* R600/SI: Implement shouldConvertConstantLoadToIntImmMatt Arsenault2014-03-314-18/+37
| | | | llvm-svn: 205244
* R600: Compute masked bits for min and maxMatt Arsenault2014-03-311-0/+44
| | | | llvm-svn: 205242
* R600: Add BFE, BFI, and BFM intrinsics to help with writing tests.Matt Arsenault2014-03-313-1/+33
| | | | llvm-svn: 205236
* R600: Add target nodes for BFM and BFIMatt Arsenault2014-03-315-3/+14
| | | | llvm-svn: 205235
* R600/SI: Implement SIInstrInfo::isTriviallyRematerializable()Tom Stellard2014-03-312-0/+15
| | | | llvm-svn: 205188
* R600/SI: Lower i64 SELECT by bitcasting to a vector typeTom Stellard2014-03-312-7/+10
| | | | | | | This allows allows us to replace ISD::EXTRACT_ELEMENT, which is lowered using shifts, with ISD::EXTRACT_VECTOR_ELT, which is a no-op. llvm-svn: 205187
* R600/SI: Return the correct index for VGPRs in getHWRegIndex()Tom Stellard2014-03-311-1/+1
| | | | | | The register index is stored in the low 8-bits of the encoding. llvm-svn: 205186
* Completely rewrite ELFObjectWriter::RecordRelocation.Rafael Espindola2014-03-291-7/+7
| | | | | | | | | | | | | | | | | | | I started trying to fix a small issue, but this code has seen a small fix too many. The old code was fairly convoluted. Some of the issues it had: * It failed to check if a symbol difference was in the some section when converting a relocation to pcrel. * It failed to check if the relocation was already pcrel. * The pcrel value computation was wrong in some cases (relocation-pc.s) * It was missing quiet a few cases where it should not convert symbol relocations to section relocations, leaving the backends to patch it up. * It would not propagate the fact that it had changed a relocation to pcrel, requiring a quiet nasty work around in ARM. * It was missing comments. llvm-svn: 205076
* R600: avoid calling std::next on an iterator that might be end()Tim Northover2014-03-281-3/+3
| | | | | | | | This was causing my llc to go into an infinite loop on CodeGen/R600/address-space.ll (just triggered recently by some allocator changes). llvm-svn: 205005
* Remove another unused argument.Rafael Espindola2014-03-271-1/+1
| | | | llvm-svn: 204961
* Remove unused argument.Rafael Espindola2014-03-271-3/+2
| | | | llvm-svn: 204956
* R600: Implement isZExtFree.Matt Arsenault2014-03-272-0/+20
| | | | | | | This allows 64-bit operations that are truncated to be reduced to 32-bit ones. llvm-svn: 204946
* R600/SI: Fix unreachable with a sext_in_reg to an illegal type.Matt Arsenault2014-03-274-4/+28
| | | | llvm-svn: 204945
* R600: Add a testcase for sext_in_reg I missed.Matt Arsenault2014-03-261-0/+2
| | | | | | This sext_inreg i32 in i64 case was already handled, but not enabled. llvm-svn: 204840
* R600: Move computeMaskedBitsForTargetNode out of AMDILISelLowering.cppMatt Arsenault2014-03-253-39/+12
| | | | | | | | Remove handling of select_cc, since it makes no sense to be there. This now does nothing, but I'll be adding some handling of other target nodes soon. llvm-svn: 204743
* R600: Don't viewCFG() under DEBUG() except on failure.Matt Arsenault2014-03-241-9/+6
| | | | | | | Having these popping up every time you use -debug is really irritating. llvm-svn: 204664
* R600/SI: Fix extra mov from legalizing 64-bit SALU ops.Matt Arsenault2014-03-241-14/+26
| | | | | | | Check the register class of each operand individually to avoid an extra copy to a vgpr. llvm-svn: 204662
* R600/SI: Sub-optimial fix for 64-bit immediates with SALU ops.Matt Arsenault2014-03-242-17/+44
| | | | | | | No longer asserts, but now you get moves loading legal immediates into the split 32-bit operations. llvm-svn: 204661
* R600/SI: Fix 64-bit bit ops that require the VALU.Matt Arsenault2014-03-243-1/+82
| | | | | | | | Try to match scalar and first like the other instructions. Expand 64-bit ands to a pair of 32-bit ands since that is not available on the VALU. llvm-svn: 204660
* R600: Implement isNarrowingProfitable.Matt Arsenault2014-03-242-0/+12
| | | | llvm-svn: 204658
* R600/SI: Move splitting 64-bit immediates to separate function.Matt Arsenault2014-03-242-39/+59
| | | | llvm-svn: 204651
* R600/SI: Fix 64-bit private loads.Matt Arsenault2014-03-241-1/+17
| | | | llvm-svn: 204630
* R600/SI: Fix warning with gcc 4.8.2Tom Stellard2014-03-241-1/+1
| | | | llvm-svn: 204618
* R600/SI: Promote fp64 SELECT to i64Tom Stellard2014-03-242-12/+2
| | | | | | | This type promotion is replacing a Tablegen pattern and it is already covered by existing tests. llvm-svn: 204617
* R600: Reorganize tablegen instruction definitionsTom Stellard2014-03-245-781/+826
| | | | | | Each GPU family now has its own file. llvm-svn: 204615
* R600/SI: Move instruction patterns to scalar versions.Matt Arsenault2014-03-212-38/+45
| | | | | | | Some of them also had the pattern on both, so this removes the duplication. llvm-svn: 204492
* R600/SI: Handle MUBUF instructions in SIInstrInfo::moveToVALU()Tom Stellard2014-03-215-4/+150
| | | | llvm-svn: 204476
* R600/SI: Handle S_MOV_B64 in SIInstrInfo::moveToVALU()Tom Stellard2014-03-211-2/+50
| | | | llvm-svn: 204475
* R600/SI: Use SGPR_(32|64) reg clases when lowering SI_ADDR64_RSRCTom Stellard2014-03-211-4/+4
| | | | | | | | | | | | | | The SReg_(32|64) register classes contain special registers in addition to the numbered SGPRs. This can lead to machine verifier errors when these register classes are used as sub-registers for SReg_128, since SReg_128 only uses the numbered SGPRs. Replacing SReg_(32|64) with SGPR_(32|64) fixes this problem, since the SGPR_(32|64) register classes contain only numbered SGPRs. Tests cases for this are comming in a later commit. llvm-svn: 204474
* R600: Remove unused method declaration.Matt Arsenault2014-03-201-6/+0
| | | | llvm-svn: 204357
* R600/SI: Add unused LDS 2 form instructions.Matt Arsenault2014-03-192-1/+35
| | | | llvm-svn: 204275
* R600/SI: Add support for 64-bit LDS writesMatt Arsenault2014-03-191-1/+4
| | | | llvm-svn: 204274
* R600/SI: Add support for 64-bit LDS loads.Matt Arsenault2014-03-191-0/+2
| | | | | | | v2: -Use correct opcode for DS_READ_64 llvm-svn: 204273
* R600/SI: Match i16 immediate offset of LDS instructions.Matt Arsenault2014-03-192-20/+39
| | | | llvm-svn: 204272
* R600/SI: Don't display the GDS bit.Matt Arsenault2014-03-191-3/+3
| | | | | | | | It isn't actually used now, and probably never will be, plus it makes tests less annoying. I also think SC prints GDS instructions as a separate instruction name. llvm-svn: 204270
* R600/SI: Merge offset0 and offset1 fields for single address DS instructions v2Matt Arsenault2014-03-192-18/+27
| | | | | | | | | Also remove unused data fields from the DS_Load_Helper class. v2: - Merge fields for DS_WRITE llvm-svn: 204269
* Make methods staticMatt Arsenault2014-03-171-23/+24
| | | | llvm-svn: 204085
* R600: Match sign_extend_inreg to BFE instructionsMatt Arsenault2014-03-179-47/+154
| | | | llvm-svn: 204072
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