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authorMatt Arsenault <Matthew.Arsenault@amd.com>2014-03-19 22:19:49 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2014-03-19 22:19:49 +0000
commit99ed78926be988798ac0973a0e15f8fa38bbcfdf (patch)
treee2fb7936d2633ba403cdad9ec222f2c89c9e5386 /llvm/lib/Target/R600
parent43eeee182a81bdcf3ea3fb8db8a3ad4e5edfaf2b (diff)
downloadbcm5719-llvm-99ed78926be988798ac0973a0e15f8fa38bbcfdf.tar.gz
bcm5719-llvm-99ed78926be988798ac0973a0e15f8fa38bbcfdf.zip
R600/SI: Match i16 immediate offset of LDS instructions.
llvm-svn: 204272
Diffstat (limited to 'llvm/lib/Target/R600')
-rw-r--r--llvm/lib/Target/R600/SIInstrInfo.td9
-rw-r--r--llvm/lib/Target/R600/SIInstructions.td50
2 files changed, 39 insertions, 20 deletions
diff --git a/llvm/lib/Target/R600/SIInstrInfo.td b/llvm/lib/Target/R600/SIInstrInfo.td
index 8973f2898c9..173f9bbd21c 100644
--- a/llvm/lib/Target/R600/SIInstrInfo.td
+++ b/llvm/lib/Target/R600/SIInstrInfo.td
@@ -99,10 +99,18 @@ def as_i32imm: SDNodeXForm<imm, [{
return CurDAG->getTargetConstant(N->getSExtValue(), MVT::i32);
}]>;
+def IMM8bit : PatLeaf <(imm),
+ [{return isUInt<8>(N->getZExtValue());}]
+>;
+
def IMM12bit : PatLeaf <(imm),
[{return isUInt<12>(N->getZExtValue());}]
>;
+def IMM16bit : PatLeaf <(imm),
+ [{return isUInt<16>(N->getZExtValue());}]
+>;
+
def mubuf_vaddr_offset : PatFrag<
(ops node:$ptr, node:$offset, node:$imm_offset),
(add (add node:$ptr, node:$offset), node:$imm_offset)
@@ -387,6 +395,7 @@ class DS_1A <bits<8> op, dag outs, dag ins, string asm, list<dag> pat> :
DS <op, outs, ins, asm, pat> {
bits<16> offset;
+ // Single load interpret the 2 i8imm operands as a single i16 offset.
let offset0 = offset{7-0};
let offset1 = offset{15-8};
}
diff --git a/llvm/lib/Target/R600/SIInstructions.td b/llvm/lib/Target/R600/SIInstructions.td
index a5b9c033ea2..3b55d427edb 100644
--- a/llvm/lib/Target/R600/SIInstructions.td
+++ b/llvm/lib/Target/R600/SIInstructions.td
@@ -1915,29 +1915,39 @@ def : Pat <
/********** Load/Store Patterns **********/
/********** ======================= **********/
-class DSReadPat <DS inst, ValueType vt, PatFrag frag> : Pat <
- (frag i32:$src0),
- (vt (inst 0, $src0, 0))
->;
+multiclass DSReadPat <DS inst, ValueType vt, PatFrag frag> {
+ def : Pat <
+ (vt (frag (add i32:$ptr, (i32 IMM16bit:$offset)))),
+ (inst (i1 0), $ptr, (as_i16imm $offset))
+ >;
-def : DSReadPat <DS_READ_I8, i32, sextloadi8_local>;
-def : DSReadPat <DS_READ_U8, i32, az_extloadi8_local>;
-def : DSReadPat <DS_READ_I16, i32, sextloadi16_local>;
-def : DSReadPat <DS_READ_U16, i32, az_extloadi16_local>;
-def : DSReadPat <DS_READ_B32, i32, local_load>;
-def : Pat <
- (local_load i32:$src0),
- (i32 (DS_READ_B32 0, $src0, 0))
->;
+ def : Pat <
+ (frag i32:$src0),
+ (vt (inst 0, $src0, 0))
+ >;
+}
-class DSWritePat <DS inst, ValueType vt, PatFrag frag> : Pat <
- (frag i32:$src1, i32:$src0),
- (inst 0, $src0, $src1, 0)
->;
+defm : DSReadPat <DS_READ_I8, i32, sextloadi8_local>;
+defm : DSReadPat <DS_READ_U8, i32, az_extloadi8_local>;
+defm : DSReadPat <DS_READ_I16, i32, sextloadi16_local>;
+defm : DSReadPat <DS_READ_U16, i32, az_extloadi16_local>;
+defm : DSReadPat <DS_READ_B32, i32, local_load>;
+
+multiclass DSWritePat <DS inst, ValueType vt, PatFrag frag> {
+ def : Pat <
+ (frag vt:$value, (add i32:$ptr, (i32 IMM16bit:$offset))),
+ (inst (i1 0), $ptr, $value, (as_i16imm $offset))
+ >;
+
+ def : Pat <
+ (frag i32:$src1, i32:$src0),
+ (inst 0, $src0, $src1, 0)
+ >;
+}
-def : DSWritePat <DS_WRITE_B8, i32, truncstorei8_local>;
-def : DSWritePat <DS_WRITE_B16, i32, truncstorei16_local>;
-def : DSWritePat <DS_WRITE_B32, i32, local_store>;
+defm : DSWritePat <DS_WRITE_B8, i32, truncstorei8_local>;
+defm : DSWritePat <DS_WRITE_B16, i32, truncstorei16_local>;
+defm : DSWritePat <DS_WRITE_B32, i32, local_store>;
def : Pat <(atomic_load_add_local i32:$ptr, i32:$val),
(DS_ADD_U32_RTN 0, $ptr, $val, 0)>;
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