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authorMatt Arsenault <Matthew.Arsenault@amd.com>2014-03-31 20:54:58 +0000
committerMatt Arsenault <Matthew.Arsenault@amd.com>2014-03-31 20:54:58 +0000
commitf751d6272d0ab6c049a383302961276c0e5fc5dc (patch)
treef6971d5b85a4bd1893701623736a170600b042d4 /llvm/lib/Target/R600
parentce5ac7d7760cf186a33a01f29e52de34713c1dd5 (diff)
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Change shouldSplitVectorElementType to better match the description.
Pass the entire vector type, and not just the element. llvm-svn: 205247
Diffstat (limited to 'llvm/lib/Target/R600')
-rw-r--r--llvm/lib/Target/R600/SIISelLowering.cpp4
-rw-r--r--llvm/lib/Target/R600/SIISelLowering.h2
2 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/R600/SIISelLowering.cpp b/llvm/lib/Target/R600/SIISelLowering.cpp
index 35bbd82af34..0b5541161ff 100644
--- a/llvm/lib/Target/R600/SIISelLowering.cpp
+++ b/llvm/lib/Target/R600/SIISelLowering.cpp
@@ -211,8 +211,8 @@ bool SITargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
return VT.bitsGT(MVT::i32);
}
-bool SITargetLowering::shouldSplitVectorElementType(EVT VT) const {
- return VT.bitsLE(MVT::i16);
+bool SITargetLowering::shouldSplitVectorType(EVT VT) const {
+ return VT.getScalarType().bitsLE(MVT::i16);
}
bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
diff --git a/llvm/lib/Target/R600/SIISelLowering.h b/llvm/lib/Target/R600/SIISelLowering.h
index 9d53ba5259d..ca73f53f222 100644
--- a/llvm/lib/Target/R600/SIISelLowering.h
+++ b/llvm/lib/Target/R600/SIISelLowering.h
@@ -50,7 +50,7 @@ class SITargetLowering : public AMDGPUTargetLowering {
public:
SITargetLowering(TargetMachine &tm);
bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AS, bool *IsFast) const;
- virtual bool shouldSplitVectorElementType(EVT VT) const;
+ virtual bool shouldSplitVectorType(EVT VT) const override;
virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
Type *Ty) const override;
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