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| author | Tom Stellard <thomas.stellard@amd.com> | 2014-03-31 14:01:52 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2014-03-31 14:01:52 +0000 |
| commit | 7277b008eed52e8a39c161f8995b8f45bf0dab5e (patch) | |
| tree | 618f9987ff2de5da72207beb07d905ebd7bf3b05 /llvm/lib/Target/R600 | |
| parent | 9b05a31f76af4ab98d9bc8ae743e9db4fff5c4b7 (diff) | |
| download | bcm5719-llvm-7277b008eed52e8a39c161f8995b8f45bf0dab5e.tar.gz bcm5719-llvm-7277b008eed52e8a39c161f8995b8f45bf0dab5e.zip | |
R600/SI: Return the correct index for VGPRs in getHWRegIndex()
The register index is stored in the low 8-bits of the encoding.
llvm-svn: 205186
Diffstat (limited to 'llvm/lib/Target/R600')
| -rw-r--r-- | llvm/lib/Target/R600/SIRegisterInfo.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/llvm/lib/Target/R600/SIRegisterInfo.cpp b/llvm/lib/Target/R600/SIRegisterInfo.cpp index a784fa42647..6cef1954935 100644 --- a/llvm/lib/Target/R600/SIRegisterInfo.cpp +++ b/llvm/lib/Target/R600/SIRegisterInfo.cpp @@ -56,7 +56,7 @@ const TargetRegisterClass * SIRegisterInfo::getCFGStructurizerRegClass( } unsigned SIRegisterInfo::getHWRegIndex(unsigned Reg) const { - return getEncodingValue(Reg); + return getEncodingValue(Reg) & 0xff; } const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const { |
