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path: root/llvm/lib/Target/R600/SILowerI1Copies.cpp
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* R600 -> AMDGPU renameTom Stellard2015-06-131-151/+0
| | | | llvm-svn: 239657
* R600/SI: Remove VReg_32 register classTom Stellard2015-01-071-1/+1
| | | | | | | | | | | Use VGPR_32 register class instead. These two register classes were identical and having separate classes was causing SIInstrInfo::isLegalOperands() to be overly conservative in some cases. This change is necessary to prevent future paches from missing a folding opportunity in fneg-fabs.ll. llvm-svn: 225382
* R600/SI: Remove i1 pseudo VALU opsMatt Arsenault2014-12-031-40/+36
| | | | | | | | | | | | | | Select i1 logical ops directly to 64-bit SALU instructions. Vector i1 values are always really in SGPRs, with each bit for each item in the wave. This saves about 4 instructions when and/or/xoring any condition, and also helps write conditions that need to be passed in vcc. This should work correctly now that the SGPR live range fixing pass works. More work is needed to eliminate the VReg_1 pseudo regclass and possibly the entire SILowerI1Copies pass. llvm-svn: 223206
* R600/SI: Create e64 versions of and/or/xor in SILowerI1CopiesMatt Arsenault2014-11-261-3/+3
| | | | | | | | | This fixes moving boolean constants into registers before operating on them. They get permuted and shrunk down to e32 anyway later. This is a temporary fix until the patch that removes these pseudos is committed. llvm-svn: 222844
* R600/SI: Fix verifier error from a branch on IMPLICIT_DEFMatt Arsenault2014-11-141-0/+8
| | | | | | SIILowerI1Copies wasn't correctly handling this case. llvm-svn: 222020
* Fix typoMatt Arsenault2014-10-091-3/+3
| | | | llvm-svn: 219429
* R600/SI: Remove modifier operands from V_CNDMASK_B32_e64Tom Stellard2014-09-221-5/+1
| | | | | | Modifiers don't work for this instruction. llvm-svn: 218253
* Remove 'virtual' keyword from methods markedwith 'override' keyword.Craig Topper2014-08-301-4/+4
| | | | llvm-svn: 216823
* Have MachineFunction cache a pointer to the subtarget to make lookupsEric Christopher2014-08-051-4/+3
| | | | | | | | | | | shorter/easier and have the DAG use that to do the same lookup. This can be used in the future for TargetMachine based caching lookups from the MachineFunction easily. Update the MIPS subtarget switching machinery to update this pointer at the same time it runs. llvm-svn: 214838
* Remove the TargetMachine forwards for TargetSubtargetInfo basedEric Christopher2014-08-041-2/+4
| | | | | | information and update all callers. No functional change. llvm-svn: 214781
* R600/SI: Do abs/neg folding with ComplexPatternsTom Stellard2014-08-011-4/+0
| | | | | | | | | | Abs/neg folding has moved out of foldOperands and into the instruction selection phase using complex patterns. As a consequence of this change, we now prefer to select the 64-bit encoding for most instructions and the modifier operands have been dropped from integer VOP3 instructions. llvm-svn: 214467
* R600/SI: Use VALU for i1 XORTom Stellard2014-07-211-0/+6
| | | | llvm-svn: 213528
* R600/SI: Use VALU instructions for i1 opsTom Stellard2014-05-151-1/+19
| | | | llvm-svn: 208885
* R600/SI: Use VALU instructions for copying i1 valuesTom Stellard2014-04-301-0/+130
We can't use SALU instructions for this since they ignore the EXEC mask and are always executed. This fixes several OpenCV tests. llvm-svn: 207661
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