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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-11-26 18:18:28 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-11-26 18:18:28 +0000 |
| commit | b9350895769de897280429e65c4840e8aeadfc54 (patch) | |
| tree | b2e9ef513e6ec341590d0f518e42ab0d5c0fcfce /llvm/lib/Target/R600/SILowerI1Copies.cpp | |
| parent | 9b9e07608d2bec926e72c812b8c4c0283ccf143b (diff) | |
| download | bcm5719-llvm-b9350895769de897280429e65c4840e8aeadfc54.tar.gz bcm5719-llvm-b9350895769de897280429e65c4840e8aeadfc54.zip | |
R600/SI: Create e64 versions of and/or/xor in SILowerI1Copies
This fixes moving boolean constants into registers before operating
on them. They get permuted and shrunk down to e32 anyway later. This
is a temporary fix until the patch that removes these pseudos is
committed.
llvm-svn: 222844
Diffstat (limited to 'llvm/lib/Target/R600/SILowerI1Copies.cpp')
| -rw-r--r-- | llvm/lib/Target/R600/SILowerI1Copies.cpp | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/lib/Target/R600/SILowerI1Copies.cpp b/llvm/lib/Target/R600/SILowerI1Copies.cpp index 65b892cf122..226a672b343 100644 --- a/llvm/lib/Target/R600/SILowerI1Copies.cpp +++ b/llvm/lib/Target/R600/SILowerI1Copies.cpp @@ -93,19 +93,19 @@ bool SILowerI1Copies::runOnMachineFunction(MachineFunction &MF) { if (MI.getOpcode() == AMDGPU::V_AND_I1) { I1Defs.push_back(MI.getOperand(0).getReg()); - MI.setDesc(TII->get(AMDGPU::V_AND_B32_e32)); + MI.setDesc(TII->get(AMDGPU::V_AND_B32_e64)); continue; } if (MI.getOpcode() == AMDGPU::V_OR_I1) { I1Defs.push_back(MI.getOperand(0).getReg()); - MI.setDesc(TII->get(AMDGPU::V_OR_B32_e32)); + MI.setDesc(TII->get(AMDGPU::V_OR_B32_e64)); continue; } if (MI.getOpcode() == AMDGPU::V_XOR_I1) { I1Defs.push_back(MI.getOperand(0).getReg()); - MI.setDesc(TII->get(AMDGPU::V_XOR_B32_e32)); + MI.setDesc(TII->get(AMDGPU::V_XOR_B32_e64)); continue; } |
