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path: root/llvm/lib/Target/R600/SIInstrInfo.td
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* R600 -> AMDGPU renameTom Stellard2015-06-131-2647/+0
* R600/SI: Add assembler support for FLAT instructionsTom Stellard2015-06-121-25/+67
* R600/SI: Add assembler support for all CI and VI VOP2 instructionsTom Stellard2015-05-261-3/+11
* R600/SI: Remove some unnecessary patterns from VINTRP multiclassTom Stellard2015-05-251-8/+4
* R600/SI: Use NAME rather than opName as the key to the MCOpcode tablesTom Stellard2015-05-251-4/+4
* R600/SI: Remove explicit m0 operand from DS instructionsTom Stellard2015-05-121-13/+112
* R600/SI: Remove explicit m0 operand from v_interp instructionsTom Stellard2015-05-121-2/+2
* Reapply r235977 "[DebugInfo] Add debug locations to constant SD nodes"Sergey Dmitrouk2015-04-281-11/+13
* Revert "[DebugInfo] Add debug locations to constant SD nodes"Daniel Jasper2015-04-281-13/+11
* [DebugInfo] Add debug locations to constant SD nodesSergey Dmitrouk2015-04-281-11/+13
* R600/SI: Add assembler support for all CI and VI VOP1 instructionsTom Stellard2015-04-231-6/+14
* R600/SI: Initial support for assembler and inline assemblyTom Stellard2015-04-081-35/+193
* R600/SI: Add missing SOPK instructionsTom Stellard2015-04-081-4/+40
* R600/SI: Fix VOP2 VI encodingMarek Olsak2015-03-271-1/+1
* R600/SI: Use V_FRACT_F64 for faster 64-bit floor on SIMarek Olsak2015-03-241-0/+1
* R600/SI: Merge tables for commutingMatt Arsenault2015-03-231-8/+3
* R600/SI: Move hasSideEffects setting into VOPCX classesMatt Arsenault2015-03-231-0/+2
* R600/SI: Allow commuting comparesMatt Arsenault2015-03-231-36/+62
* R600/SI: Remove cond operand to VOPCX classesMatt Arsenault2015-03-231-8/+8
* R600/SI: Refactor VOP2 instruction defsTom Stellard2015-03-201-6/+13
* R600/SI: Refactor VOP1 instruction defsTom Stellard2015-03-201-7/+12
* R600/SI: Don't print scc reg in sopc assembly stringTom Stellard2015-03-121-1/+1
* R600/SI: Remove _e32 and _e64 suffixes from mnemonicsTom Stellard2015-03-121-23/+25
* R600/SI: Add _IDXEN and _BOTHEN variants for buffer_storeTom Stellard2015-03-101-0/+15
* R600/SI: Re-order MUBUF operands to match asm strings.Tom Stellard2015-03-101-8/+8
* R600/SI: Add 32-bit encoding of v_cndmask_b32Tom Stellard2015-03-101-0/+5
* R600/SI: Move gds operand to the end of operand listTom Stellard2015-03-091-23/+26
* R600/SI: Refactor DS instruction defsTom Stellard2015-03-091-169/+95
* R600/SI: Fix DS definitions and add missing instructionsTom Stellard2015-03-091-2/+60
* R600/SI: Add missing mubuf instructionsTom Stellard2015-02-271-1/+1
* R600/SI: Consistently put soffset before the offset operand for mubuf instruc...Tom Stellard2015-02-271-16/+16
* R600/SI: Add slc, glc, and tfe to non-atomic _ADDR64 instructionsTom Stellard2015-02-271-10/+16
* R600/SI: Remove M0 from DS assembly stringsTom Stellard2015-02-261-8/+8
* R600/SI: Fix mad*k definitionsMatt Arsenault2015-02-211-0/+21
* R600/SI: Don't set isCodeGenOnly = 1 on all instructionsTom Stellard2015-02-181-2/+14
* R600/SI: Add missing VOP1 instructionsTom Stellard2015-02-181-0/+3
* R600/SI: Add definition for S_CBRANCH_G_FORKTom Stellard2015-02-181-0/+6
* R600/SI: Add missing SOP1 instructionsTom Stellard2015-02-181-0/+15
* R600/SI: Refactor SOP2 definitionsTom Stellard2015-02-181-25/+17
* R600/SI: Consistently capitalize encoding field namesMatt Arsenault2015-02-181-3/+3
* R600/SI: Fix src1_modifiers for class instructionsMatt Arsenault2015-02-181-2/+26
* R600/SI: Fix not setting clamp / omod for v_cndmask_b32_e64Matt Arsenault2015-02-181-2/+4
* R600/SI: Fix encoding error from glc bit on VI SMRD instructionsMatt Arsenault2015-02-181-1/+5
* R600/SI: Fix operand encoding for flat instructionsMatt Arsenault2015-02-181-2/+4
* R600/SI: Fix error from vdst on no return atomicsMatt Arsenault2015-02-181-3/+5
* R600/SI: Add missing offset operand to buffer bothenMatt Arsenault2015-02-181-2/+2
* R600/SI: Add missing soffset operand to global atomicsMatt Arsenault2015-02-181-2/+2
* R600/SI: Fix implicit vcc operand to v_div_fmas_*Matt Arsenault2015-02-141-0/+22
* R600/SI: Fix not encoding src2 for v_div_scale_{f32|f64}Matt Arsenault2015-02-141-1/+14
* R600/SI: Fix VOP3b encoding on VIMatt Arsenault2015-02-141-8/+17
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