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* R600 -> AMDGPU renameTom Stellard2015-06-131-2647/+0
| | | | llvm-svn: 239657
* R600/SI: Add assembler support for FLAT instructionsTom Stellard2015-06-121-25/+67
| | | | | | | | - Add glc, slc, and tfe operands to flat instructions - Add missing flat instructions - Fix the encoding of flat_load_dwordx3 and flat_store_dwordx3. llvm-svn: 239637
* R600/SI: Add assembler support for all CI and VI VOP2 instructionsTom Stellard2015-05-261-3/+11
| | | | llvm-svn: 238211
* R600/SI: Remove some unnecessary patterns from VINTRP multiclassTom Stellard2015-05-251-8/+4
| | | | | | | DisableEncoding and Constraints can be set using let statements around the multiclass defs. llvm-svn: 238148
* R600/SI: Use NAME rather than opName as the key to the MCOpcode tablesTom Stellard2015-05-251-4/+4
| | | | | | | | This lets us drop a parameter the opName parameter to the VINTRP multiclass and makes it possible to create multiple VINTRP defs with the same asm mnemonic. llvm-svn: 238146
* R600/SI: Remove explicit m0 operand from DS instructionsTom Stellard2015-05-121-13/+112
| | | | | | | Instead add m0 as an implicit operand. This helps avoid spills of the m0 register in some cases. llvm-svn: 237141
* R600/SI: Remove explicit m0 operand from v_interp instructionsTom Stellard2015-05-121-2/+2
| | | | | | | Instead add m0 as an implicit operand. This helps avoid spills of the m0 register in some cases. llvm-svn: 237140
* Reapply r235977 "[DebugInfo] Add debug locations to constant SD nodes"Sergey Dmitrouk2015-04-281-11/+13
| | | | | | | | | | | | | | | | | | | | | | | | | [DebugInfo] Add debug locations to constant SD nodes This adds debug location to constant nodes of Selection DAG and updates all places that create constants to pass debug locations (see PR13269). Can't guarantee that all locations are correct, but in a lot of cases choice is obvious, so most of them should be. At least all tests pass. Tests for these changes do not cover everything, instead just check it for SDNodes, ARM and AArch64 where it's easy to get incorrect locations on constants. This is not complete fix as FastISel contains workaround for wrong debug locations, which drops locations from instructions on processing constants, but there isn't currently a way to use debug locations from constants there as llvm::Constant doesn't cache it (yet). Although this is a bit different issue, not directly related to these changes. Differential Revision: http://reviews.llvm.org/D9084 llvm-svn: 235989
* Revert "[DebugInfo] Add debug locations to constant SD nodes"Daniel Jasper2015-04-281-13/+11
| | | | | | | This breaks a test: http://bb.pgr.jp/builders/cmake-llvm-x86_64-linux/builds/23870 llvm-svn: 235987
* [DebugInfo] Add debug locations to constant SD nodesSergey Dmitrouk2015-04-281-11/+13
| | | | | | | | | | | | | | | | | | | | | | | This adds debug location to constant nodes of Selection DAG and updates all places that create constants to pass debug locations (see PR13269). Can't guarantee that all locations are correct, but in a lot of cases choice is obvious, so most of them should be. At least all tests pass. Tests for these changes do not cover everything, instead just check it for SDNodes, ARM and AArch64 where it's easy to get incorrect locations on constants. This is not complete fix as FastISel contains workaround for wrong debug locations, which drops locations from instructions on processing constants, but there isn't currently a way to use debug locations from constants there as llvm::Constant doesn't cache it (yet). Although this is a bit different issue, not directly related to these changes. Differential Revision: http://reviews.llvm.org/D9084 llvm-svn: 235977
* R600/SI: Add assembler support for all CI and VI VOP1 instructionsTom Stellard2015-04-231-6/+14
| | | | llvm-svn: 235629
* R600/SI: Initial support for assembler and inline assemblyTom Stellard2015-04-081-35/+193
| | | | | | | | | | | | | This is currently considered experimental, but most of the more commonly used instructions should work. So far only SI has been extensively tested, CI and VI probably work too, but may be buggy. The current set of tests cases do not give complete coverage, but I think it is sufficient for an experimental assembler. See the documentation in R600Usage for more information. llvm-svn: 234381
* R600/SI: Add missing SOPK instructionsTom Stellard2015-04-081-4/+40
| | | | llvm-svn: 234380
* R600/SI: Fix VOP2 VI encodingMarek Olsak2015-03-271-1/+1
| | | | | | Broken by "R600/SI: Refactor VOP2 instruction defs". llvm-svn: 233399
* R600/SI: Use V_FRACT_F64 for faster 64-bit floor on SIMarek Olsak2015-03-241-0/+1
| | | | | | | Other f64 opcodes not supported on SI can be lowered in a similar way. v2: use complex VOP3 patterns llvm-svn: 233076
* R600/SI: Merge tables for commutingMatt Arsenault2015-03-231-8/+3
| | | | | | | Don't use a separate table for compares anymore, and use the same VOP2_REV class. llvm-svn: 232992
* R600/SI: Move hasSideEffects setting into VOPCX classesMatt Arsenault2015-03-231-0/+2
| | | | llvm-svn: 232989
* R600/SI: Allow commuting comparesMatt Arsenault2015-03-231-36/+62
| | | | | | | | | | | | | | | | | This enables very common cases to switch to the smaller encoding. All of the standard LLVM canonicalizations of comparisons are the opposite of what we want. Compares with constants are moved to the RHS, but the first operand can be an inline immediate, literal constant, or SGPR using the 32-bit VOPC encoding. There are additional bad canonicalizations that should also be fixed, such as canonicalizing ge x, k to gt x, (k + 1) if this makes k no longer an inline immediate value. llvm-svn: 232988
* R600/SI: Remove cond operand to VOPCX classesMatt Arsenault2015-03-231-8/+8
| | | | | | It isn't used, and these will probably never be directly selected. llvm-svn: 232986
* R600/SI: Refactor VOP2 instruction defsTom Stellard2015-03-201-6/+13
| | | | llvm-svn: 232817
* R600/SI: Refactor VOP1 instruction defsTom Stellard2015-03-201-7/+12
| | | | llvm-svn: 232816
* R600/SI: Don't print scc reg in sopc assembly stringTom Stellard2015-03-121-1/+1
| | | | | | This is how the proprietary driver prints sopc instructions. llvm-svn: 232106
* R600/SI: Remove _e32 and _e64 suffixes from mnemonicsTom Stellard2015-03-121-23/+25
| | | | | | | | Instead print them as part of the $dst operand. The AsmMatcher requires the 32-bit and 64-bit encodings have the same mnemonic in order to parse them correctly. llvm-svn: 232105
* R600/SI: Add _IDXEN and _BOTHEN variants for buffer_storeTom Stellard2015-03-101-0/+15
| | | | llvm-svn: 231798
* R600/SI: Re-order MUBUF operands to match asm strings.Tom Stellard2015-03-101-8/+8
| | | | llvm-svn: 231797
* R600/SI: Add 32-bit encoding of v_cndmask_b32Tom Stellard2015-03-101-0/+5
| | | | | | | This was done by refactoring the v_cndmask_b32 tablegen definition to use inherit from VOP2Inst. llvm-svn: 231795
* R600/SI: Move gds operand to the end of operand listTom Stellard2015-03-091-23/+26
| | | | | | Also print it in the assembly string. llvm-svn: 231684
* R600/SI: Refactor DS instruction defsTom Stellard2015-03-091-169/+95
| | | | llvm-svn: 231683
* R600/SI: Fix DS definitions and add missing instructionsTom Stellard2015-03-091-2/+60
| | | | llvm-svn: 231663
* R600/SI: Add missing mubuf instructionsTom Stellard2015-02-271-1/+1
| | | | llvm-svn: 230759
* R600/SI: Consistently put soffset before the offset operand for mubuf ↵Tom Stellard2015-02-271-16/+16
| | | | | | | | instructions This matches the assembly syntax. llvm-svn: 230758
* R600/SI: Add slc, glc, and tfe to non-atomic _ADDR64 instructionsTom Stellard2015-02-271-10/+16
| | | | llvm-svn: 230757
* R600/SI: Remove M0 from DS assembly stringsTom Stellard2015-02-261-8/+8
| | | | | | This matches the assembly syntax for the proprietary compiler. llvm-svn: 230645
* R600/SI: Fix mad*k definitionsMatt Arsenault2015-02-211-0/+21
| | | | llvm-svn: 230146
* R600/SI: Don't set isCodeGenOnly = 1 on all instructionsTom Stellard2015-02-181-2/+14
| | | | | | | We only need to set this on pseudo instructions which won't be used by the assembler. llvm-svn: 229689
* R600/SI: Add missing VOP1 instructionsTom Stellard2015-02-181-0/+3
| | | | llvm-svn: 229688
* R600/SI: Add definition for S_CBRANCH_G_FORKTom Stellard2015-02-181-0/+6
| | | | llvm-svn: 229686
* R600/SI: Add missing SOP1 instructionsTom Stellard2015-02-181-0/+15
| | | | llvm-svn: 229685
* R600/SI: Refactor SOP2 definitionsTom Stellard2015-02-181-25/+17
| | | | llvm-svn: 229684
* R600/SI: Consistently capitalize encoding field namesMatt Arsenault2015-02-181-3/+3
| | | | | | | | | | Some formats capitalized these, but most didn't. Change them all to be consistently lowercase. Now, non-encoding fields and convenience bits are capitalized. Also remove weird looking empty line in some of the formats. llvm-svn: 229613
* R600/SI: Fix src1_modifiers for class instructionsMatt Arsenault2015-02-181-2/+26
| | | | | | | | src1 doesn't have modifiers, but the operand was missing resulting in an encoding build error when all fields are required.' llvm-svn: 229611
* R600/SI: Fix not setting clamp / omod for v_cndmask_b32_e64Matt Arsenault2015-02-181-2/+4
| | | | | | | Rename the multiclass since it now applies to the output modifiers as well. llvm-svn: 229610
* R600/SI: Fix encoding error from glc bit on VI SMRD instructionsMatt Arsenault2015-02-181-1/+5
| | | | llvm-svn: 229608
* R600/SI: Fix operand encoding for flat instructionsMatt Arsenault2015-02-181-2/+4
| | | | llvm-svn: 229607
* R600/SI: Fix error from vdst on no return atomicsMatt Arsenault2015-02-181-3/+5
| | | | | | | Set the ignored field to 0 so we can enable noNamedPositionallyEncodedOperands. llvm-svn: 229606
* R600/SI: Add missing offset operand to buffer bothenMatt Arsenault2015-02-181-2/+2
| | | | llvm-svn: 229605
* R600/SI: Add missing soffset operand to global atomicsMatt Arsenault2015-02-181-2/+2
| | | | llvm-svn: 229604
* R600/SI: Fix implicit vcc operand to v_div_fmas_*Matt Arsenault2015-02-141-0/+22
| | | | | | | | | This should allow finally fixing the f64 fdiv implementation. Test is disabled for VI since there seems to be a problem with one of the buffer load instructions on it. llvm-svn: 229236
* R600/SI: Fix not encoding src2 for v_div_scale_{f32|f64}Matt Arsenault2015-02-141-1/+14
| | | | | | This apparently got lost in the VI changes. llvm-svn: 229230
* R600/SI: Fix VOP3b encoding on VIMatt Arsenault2015-02-141-8/+17
| | | | llvm-svn: 229228
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