summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/R600/SIInstrInfo.h
Commit message (Expand)AuthorAgeFilesLines
* R600 -> AMDGPU renameTom Stellard2015-06-131-391/+0
* R600/SI: Fix bug in VGPR spillingTom Stellard2015-05-121-0/+4
* MachineCSE: Add a target query for the LookAheadLimit heurisiticTom Stellard2015-05-091-0/+2
* R600/SI: Special case v_mov_b32 as really rematerializableMatt Arsenault2015-04-231-0/+3
* R600/SI: Merge tables for commutingMatt Arsenault2015-03-231-4/+0
* R600/SI: Allow commuting comparesMatt Arsenault2015-03-231-1/+5
* Remove the need to cache the subtarget in the R600 TargetRegisterInfoEric Christopher2015-03-111-4/+0
* R600/SI: Try to use v_madak_f32Matt Arsenault2015-02-211-0/+3
* R600/SI: Don't crash when getting immediate operand sizeMatt Arsenault2015-02-211-0/+7
* R600/SI: Allow f64 inline immediates in i64 operandsMatt Arsenault2015-02-131-4/+18
* R600/SI: Also enable WQM for image opcodes which calculate LOD v3Michel Danzer2015-02-061-0/+4
* R600/SI: Don't shrink instructions whose e32 encoding doesn't existMarek Olsak2015-01-151-1/+0
* R600/SI: Teach SIFoldOperands to split 64-bit constants when foldingTom Stellard2015-01-071-0/+4
* R600/SI: Set 20-bit immediate byte offset for SMRD on VIMarek Olsak2014-12-071-1/+1
* R600/SI: Update instruction conversions for VIMarek Olsak2014-12-071-0/+2
* R600/SI: Set the ATC bit on all resource descriptors for the HSA runtimeTom Stellard2014-12-021-0/+3
* R600/SI: Various instruction format bit test cleanupsMatt Arsenault2014-12-011-11/+69
* R600/SI: Implement areMemAccessesTriviallyDisjointMatt Arsenault2014-11-191-0/+8
* R600/SI: Use S_BFE_I64 for 64-bit sext_inregMatt Arsenault2014-11-141-0/+2
* R600/SI: Fix general commuting breaking src modsMatt Arsenault2014-10-171-0/+9
* R600/SI: Fix hardcoded values for modifiers.Matt Arsenault2014-09-291-16/+0
* R600/SI: Move finding SGPR operand to move to separate functionMatt Arsenault2014-09-261-0/+2
* R600/SI: Implement findCommutedOpIndicesMatt Arsenault2014-09-261-1/+4
* R600/SI: Implement VGPR register spilling for compute at -O0 v3Tom Stellard2014-09-241-0/+7
* R600/SI: Clean up checks for legality of immediate operandsTom Stellard2014-09-231-0/+4
* R600/SI: Add enums for some hard-coded valuesTom Stellard2014-09-221-0/+19
* R600/SI: Rough first implementation of shouldClusterLoadsMatt Arsenault2014-09-171-0/+4
* R600/SI: Add preliminary support for flat address spaceMatt Arsenault2014-09-151-0/+1
* R600/SI: Add InstrMapping for noret atomics.Matt Arsenault2014-09-081-0/+2
* Add override to overriden virtual methods, remove virtual keywords.Benjamin Kramer2014-09-031-1/+1
* R600/SI: Teach moveToVALU how to handle more S_LOAD_* instructionsTom Stellard2014-08-211-0/+6
* R600/SI: Fix offset folding in some cases with shifted pointers.Matt Arsenault2014-08-151-0/+4
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-131-3/+3
* R600/SI: Add a ComplexPattern for selecting MUBUF _OFFSET variantTom Stellard2014-08-111-0/+1
* R600/SI: Implement areLoadsFromSameBasePtrMatt Arsenault2014-08-061-0/+4
* R600/SI: Do abs/neg folding with ComplexPatternsTom Stellard2014-08-011-0/+10
* R600/SI: Simplify and fix handling of VOP2 in SIInstrInfo::legalizeOperandsTom Stellard2014-08-011-0/+5
* R600/SI: Fold immediates when shrinking instructionsTom Stellard2014-08-011-2/+1
* R600/SI: Fix incorrect commute operation in shrink instructions passTom Stellard2014-08-011-0/+4
* R600/SI: Implement getLdStBaseRegImmOfsMatt Arsenault2014-07-291-0/+4
* R600/SI: Add isMUBUF / isMTBUFMatt Arsenault2014-07-291-0/+2
* R600/SI: Fix return type for isMIMG / isSMRDMatt Arsenault2014-07-281-2/+2
* R600/SI: Add instruction shrinking passTom Stellard2014-07-211-0/+6
* R600/SI: Use scratch memory for large private arraysTom Stellard2014-07-211-1/+4
* R600: Remove unused functionMatt Arsenault2014-07-201-4/+0
* R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtargetTom Stellard2014-06-131-1/+1
* R600/SI: Implement i64 ctpopMatt Arsenault2014-06-101-0/+3
* R600/SI: Keep 64-bit not on SALUMatt Arsenault2014-06-091-2/+5
* R600/SI: Refactor the VOP3_32 tablegen classTom Stellard2014-05-161-0/+1
* R600/SI: Only create one instruction when spilling/restoring register v3Tom Stellard2014-05-021-0/+4
OpenPOWER on IntegriCloud