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* R600 -> AMDGPU renameTom Stellard2015-06-131-391/+0
| | | | llvm-svn: 239657
* R600/SI: Fix bug in VGPR spillingTom Stellard2015-05-121-0/+4
| | | | | | | | | | | | AMDGPU::SI_SPILL_V96_RESTORE was missing from a switch statement, which caused the srsrc and soffset register to not be set correctly. This commit replaces the switch statement with a SITargetInfo query to make sure all spill instructions are covered. Differential Revision: http://reviews.llvm.org/D9582 llvm-svn: 237164
* MachineCSE: Add a target query for the LookAheadLimit heurisiticTom Stellard2015-05-091-0/+2
| | | | | | | | | This is used to determine whether or not to CSE physical register defs. Differential Revision: http://reviews.llvm.org/D9472 llvm-svn: 236923
* R600/SI: Special case v_mov_b32 as really rematerializableMatt Arsenault2015-04-231-0/+3
| | | | | | | This should be fixed to properly understand all rematerializable instructions while ignoring implicit reads of exec. llvm-svn: 235671
* R600/SI: Merge tables for commutingMatt Arsenault2015-03-231-4/+0
| | | | | | | Don't use a separate table for compares anymore, and use the same VOP2_REV class. llvm-svn: 232992
* R600/SI: Allow commuting comparesMatt Arsenault2015-03-231-1/+5
| | | | | | | | | | | | | | | | | This enables very common cases to switch to the smaller encoding. All of the standard LLVM canonicalizations of comparisons are the opposite of what we want. Compares with constants are moved to the RHS, but the first operand can be an inline immediate, literal constant, or SGPR using the 32-bit VOPC encoding. There are additional bad canonicalizations that should also be fixed, such as canonicalizing ge x, k to gt x, (k + 1) if this makes k no longer an inline immediate value. llvm-svn: 232988
* Remove the need to cache the subtarget in the R600 TargetRegisterInfoEric Christopher2015-03-111-4/+0
| | | | | | classes. llvm-svn: 231954
* R600/SI: Try to use v_madak_f32Matt Arsenault2015-02-211-0/+3
| | | | | | | This is a code size optimization when the constant only has one use. llvm-svn: 230148
* R600/SI: Don't crash when getting immediate operand sizeMatt Arsenault2015-02-211-0/+7
| | | | llvm-svn: 230147
* R600/SI: Allow f64 inline immediates in i64 operandsMatt Arsenault2015-02-131-4/+18
| | | | | | | This requires considering the size of the operand when checking immediate legality. llvm-svn: 229135
* R600/SI: Also enable WQM for image opcodes which calculate LOD v3Michel Danzer2015-02-061-0/+4
| | | | | | | | | | | | | If whole quad mode isn't enabled for these, the level of detail is calculated incorrectly for pixels along diagonal triangle edges, causing artifacts. v2: Use a TSFlag instead of lots of switch cases v3: Add test coverage Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88642 Reviewed-by: Tom Stellard <tom@stellard.net> llvm-svn: 228372
* R600/SI: Don't shrink instructions whose e32 encoding doesn't existMarek Olsak2015-01-151-1/+0
| | | | | | | | v2: modify hasVALU32BitEncoding instead v3: - add pseudoToMCOpcode helper to AMDGPUInstInfo, which is used by both hasVALU32BitEncoding and AMDGPUMCInstLower::lower - report an error if a pseudo can't be lowered llvm-svn: 226188
* R600/SI: Teach SIFoldOperands to split 64-bit constants when foldingTom Stellard2015-01-071-0/+4
| | | | | | | | | | | | | | | This allows folding of sequences like: s[0:1] = s_mov_b64 4 v_add_i32 v0, s0, v0 v_addc_u32 v1, s1, v1 into v_add_i32 v0, 4, v0 v_add_i32 v1, 0, v1 llvm-svn: 225369
* R600/SI: Set 20-bit immediate byte offset for SMRD on VIMarek Olsak2014-12-071-1/+1
| | | | llvm-svn: 223614
* R600/SI: Update instruction conversions for VIMarek Olsak2014-12-071-0/+2
| | | | | | | | | There are 3 changes: - Convert 32-bit S_LSHL/LSHR/ASHR to their V_*REV variants for VI - Lower RSQ_CLAMP for VI - Don't generate MIN/MAX_LEGACY on VI llvm-svn: 223604
* R600/SI: Set the ATC bit on all resource descriptors for the HSA runtimeTom Stellard2014-12-021-0/+3
| | | | llvm-svn: 223125
* R600/SI: Various instruction format bit test cleanupsMatt Arsenault2014-12-011-11/+69
| | | | | | | | | | | - Fix missing SALU format bits - Remove unused isSALUInstr - Add isVALU - Switch isDS to use a bit like the others - Move SIInstrInfo::is* functions to header - Reorder so they are approximately sorted by type (SALU, VALU, memory) llvm-svn: 223038
* R600/SI: Implement areMemAccessesTriviallyDisjointMatt Arsenault2014-11-191-0/+8
| | | | | | | | | This partially makes up for not having address spaces used for alias analysis in some simple cases. This is not yet enabled by default so shouldn't change anything yet. llvm-svn: 222286
* R600/SI: Use S_BFE_I64 for 64-bit sext_inregMatt Arsenault2014-11-141-0/+2
| | | | llvm-svn: 222012
* R600/SI: Fix general commuting breaking src modsMatt Arsenault2014-10-171-0/+9
| | | | | | | | The generic code trying to use findCommutedOpIndices won't understand that it needs to swap the modifier operands also, so it should fail if they are set. llvm-svn: 220064
* R600/SI: Fix hardcoded values for modifiers.Matt Arsenault2014-09-291-16/+0
| | | | | | Move enums to SIDefines.h llvm-svn: 218610
* R600/SI: Move finding SGPR operand to move to separate functionMatt Arsenault2014-09-261-0/+2
| | | | llvm-svn: 218533
* R600/SI: Implement findCommutedOpIndicesMatt Arsenault2014-09-261-1/+4
| | | | | | | | | | | The base implementation of commuteInstruction is used in some cases, but it turns out this has been broken for a long time since modifiers were inserted between the real operands. The base implementation of commuteInstruction also fails on immediates, which also needs to be fixed. llvm-svn: 218530
* R600/SI: Implement VGPR register spilling for compute at -O0 v3Tom Stellard2014-09-241-0/+7
| | | | | | | | | | | | | | VGPRs are spilled to LDS. This still needs more testing, but we need to at least enable it at -O0, because the fast register allocator spills all registers that are live at the end of blocks and without this some future commits will break the flat-address-space.ll test. v2: Only calculate thread id once v3: Move insertion of spill instructions to SIRegisterInfo::eliminateFrameIndex() llvm-svn: 218348
* R600/SI: Clean up checks for legality of immediate operandsTom Stellard2014-09-231-0/+4
| | | | | | | | | | | | | | There are new register classes VCSrc_* which represent operands that can take an SGPR, VGPR or inline constant. The VSrc_* class is now used to represent operands that can take an SGPR, VGPR, or a 32-bit immediate. This allows us to have more accurate checks for legality of immediates, since before we had no way to distinguish between operands that supported any 32-bit immediate and operands which could only support inline constants. llvm-svn: 218334
* R600/SI: Add enums for some hard-coded valuesTom Stellard2014-09-221-0/+19
| | | | llvm-svn: 218250
* R600/SI: Rough first implementation of shouldClusterLoadsMatt Arsenault2014-09-171-0/+4
| | | | llvm-svn: 217968
* R600/SI: Add preliminary support for flat address spaceMatt Arsenault2014-09-151-0/+1
| | | | llvm-svn: 217777
* R600/SI: Add InstrMapping for noret atomics.Matt Arsenault2014-09-081-0/+2
| | | | | | | | Only handles LDS atomics for now, and will be used to replace atomics with no uses with the no return versions. llvm-svn: 217378
* Add override to overriden virtual methods, remove virtual keywords.Benjamin Kramer2014-09-031-1/+1
| | | | | | No functionality change. Changes made by clang-tidy + some manual cleanup. llvm-svn: 217028
* R600/SI: Teach moveToVALU how to handle more S_LOAD_* instructionsTom Stellard2014-08-211-0/+6
| | | | llvm-svn: 216220
* R600/SI: Fix offset folding in some cases with shifted pointers.Matt Arsenault2014-08-151-0/+4
| | | | | | | | | | | | | Ordinarily (shl (add x, c1), c2) -> (add (shl x, c2), c1 << c2) is only done if the add has one use. If the resulting constant add can be folded into an addressing mode, force this to happen for the pointer operand. This ends up happening a lot because of how LDS objects are allocated. Since the globals are allocated next to each other, acessing the first element of the second object is directly indexed by a shifted pointer. llvm-svn: 215739
* Canonicalize header guards into a common format.Benjamin Kramer2014-08-131-3/+3
| | | | | | | | | | Add header guards to files that were missing guards. Remove #endif comments as they don't seem common in LLVM (we can easily add them back if we decide they're useful) Changes made by clang-tidy with minor tweaks. llvm-svn: 215558
* R600/SI: Add a ComplexPattern for selecting MUBUF _OFFSET variantTom Stellard2014-08-111-0/+1
| | | | | | | This saves us from having to copy a 64-bit 0 value into VGPRs for BUFFER_* instruction which only have a 12-bit immediate offset. llvm-svn: 215399
* R600/SI: Implement areLoadsFromSameBasePtrMatt Arsenault2014-08-061-0/+4
| | | | | | | | This currently has a noticable effect on the kernel argument loads. LDS and global loads are more problematic, I think because of how copies are currently inserted to ensure that the address is a VGPR. llvm-svn: 214942
* R600/SI: Do abs/neg folding with ComplexPatternsTom Stellard2014-08-011-0/+10
| | | | | | | | | | Abs/neg folding has moved out of foldOperands and into the instruction selection phase using complex patterns. As a consequence of this change, we now prefer to select the 64-bit encoding for most instructions and the modifier operands have been dropped from integer VOP3 instructions. llvm-svn: 214467
* R600/SI: Simplify and fix handling of VOP2 in SIInstrInfo::legalizeOperandsTom Stellard2014-08-011-0/+5
| | | | | | | | | | | | We were incorrectly assuming that all VOP2 instructions can read SGPRs in Src0, but this is not true for instructions that read carry-in from VCC. The old logic has been replaced with new logic which checks the defined register classes of the VOP2 instruction to determine whether or not to legalize the operands. llvm-svn: 214465
* R600/SI: Fold immediates when shrinking instructionsTom Stellard2014-08-011-2/+1
| | | | | | | This will prevent us from using extra MOV instructions once we prefer selecting 64-bit instructions. llvm-svn: 214464
* R600/SI: Fix incorrect commute operation in shrink instructions passTom Stellard2014-08-011-0/+4
| | | | | | | | We were commuting the instruction by still shrinking it using the original opcode. NOTE: This is a candidate for the 3.5 branch. llvm-svn: 214463
* R600/SI: Implement getLdStBaseRegImmOfsMatt Arsenault2014-07-291-0/+4
| | | | llvm-svn: 214225
* R600/SI: Add isMUBUF / isMTBUFMatt Arsenault2014-07-291-0/+2
| | | | | | Also add missing comments about how the flags work. llvm-svn: 214195
* R600/SI: Fix return type for isMIMG / isSMRDMatt Arsenault2014-07-281-2/+2
| | | | | | All the others use bool, so these should too. llvm-svn: 214106
* R600/SI: Add instruction shrinking passTom Stellard2014-07-211-0/+6
| | | | | | This pass converts 64-bit instructions to 32-bit when possible. llvm-svn: 213561
* R600/SI: Use scratch memory for large private arraysTom Stellard2014-07-211-1/+4
| | | | llvm-svn: 213551
* R600: Remove unused functionMatt Arsenault2014-07-201-4/+0
| | | | llvm-svn: 213472
* R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtargetTom Stellard2014-06-131-1/+1
| | | | llvm-svn: 210869
* R600/SI: Implement i64 ctpopMatt Arsenault2014-06-101-0/+3
| | | | llvm-svn: 210568
* R600/SI: Keep 64-bit not on SALUMatt Arsenault2014-06-091-2/+5
| | | | llvm-svn: 210476
* R600/SI: Refactor the VOP3_32 tablegen classTom Stellard2014-05-161-0/+1
| | | | | | | | This will allow us to use a single MachineInstr to represent instructions which behave the same but have different encodings on some subtargets. llvm-svn: 209028
* R600/SI: Only create one instruction when spilling/restoring register v3Tom Stellard2014-05-021-0/+4
| | | | | | | | | | | | | | | | | | The register spiller assumes that only one new instruction is created when spilling and restoring registers, so we need to emit pseudo instructions for vector register spills and lower them after register allocation. v2: - Fix calculation of lane index - Extend VGPR liveness to end of program. v3: - Use SIMM16 field of S_NOP to specify multiple NOPs. https://bugs.freedesktop.org/show_bug.cgi?id=75005 llvm-svn: 207843
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