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path: root/llvm/lib/Target/R600/SIInstrInfo.cpp
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* R600/SI: Use eliminateFrameIndex() to expand SGPR spill pseudosTom Stellard2014-08-211-98/+11
| | | | | | | | | | | | | | | This will simplify the SGPR spilling and also allow us to use MachineFrameInfo for calculating offsets, which should be more reliable than our custom code. This fixes a crash in some cases where a register would be spilled in a branch such that the VGPR defined for spilling did not dominate all the uses when restoring. This fixes a crash in an ocl conformance test. The test requries register spilling and is too big to include. llvm-svn: 216217
* R600/SI: Fix offset folding in some cases with shifted pointers.Matt Arsenault2014-08-151-0/+22
| | | | | | | | | | | | | Ordinarily (shl (add x, c1), c2) -> (add (shl x, c2), c1 << c2) is only done if the add has one use. If the resulting constant add can be folded into an addressing mode, force this to happen for the pointer operand. This ends up happening a lot because of how LDS objects are allocated. Since the globals are allocated next to each other, acessing the first element of the second object is directly indexed by a shifted pointer. llvm-svn: 215739
* R600/SIInstrInfo.cpp: Suppress an warning. [-Wunused-variable]NAKAMURA Takumi2014-08-111-0/+1
| | | | llvm-svn: 215406
* R600/SI: Add a ComplexPattern for selecting MUBUF _OFFSET variantTom Stellard2014-08-111-103/+156
| | | | | | | This saves us from having to copy a 64-bit 0 value into VGPRs for BUFFER_* instruction which only have a 12-bit immediate offset. llvm-svn: 215399
* R600/SI: Implement areLoadsFromSameBasePtrMatt Arsenault2014-08-061-0/+98
| | | | | | | | This currently has a noticable effect on the kernel argument loads. LDS and global loads are more problematic, I think because of how copies are currently inserted to ensure that the address is a VGPR. llvm-svn: 214942
* R600/SI: Do abs/neg folding with ComplexPatternsTom Stellard2014-08-011-24/+30
| | | | | | | | | | Abs/neg folding has moved out of foldOperands and into the instruction selection phase using complex patterns. As a consequence of this change, we now prefer to select the 64-bit encoding for most instructions and the modifier operands have been dropped from integer VOP3 instructions. llvm-svn: 214467
* R600/SI: Simplify and fix handling of VOP2 in SIInstrInfo::legalizeOperandsTom Stellard2014-08-011-28/+48
| | | | | | | | | | | | We were incorrectly assuming that all VOP2 instructions can read SGPRs in Src0, but this is not true for instructions that read carry-in from VCC. The old logic has been replaced with new logic which checks the defined register classes of the VOP2 instruction to determine whether or not to legalize the operands. llvm-svn: 214465
* R600/SI: Fold immediates when shrinking instructionsTom Stellard2014-08-011-1/+1
| | | | | | | This will prevent us from using extra MOV instructions once we prefer selecting 64-bit instructions. llvm-svn: 214464
* R600/SI: Fix incorrect commute operation in shrink instructions passTom Stellard2014-08-011-0/+4
| | | | | | | | We were commuting the instruction by still shrinking it using the original opcode. NOTE: This is a candidate for the 3.5 branch. llvm-svn: 214463
* R600/SI: Consider adjacent offsets in getLdStBaseRegImmOfsMatt Arsenault2014-07-301-13/+39
| | | | | | | | | We can treat ds_read2_* as a single offset if the offsets are adjacent. No test since emission of read2 instructions for partially aligned loads isn't implemented yet. llvm-svn: 214269
* R600/SI: Implement getLdStBaseRegImmOfsMatt Arsenault2014-07-291-0/+58
| | | | llvm-svn: 214225
* R600/SI: Add isMUBUF / isMTBUFMatt Arsenault2014-07-291-0/+8
| | | | | | Also add missing comments about how the flags work. llvm-svn: 214195
* Fix typos / grammar.Matt Arsenault2014-07-291-1/+1
| | | | llvm-svn: 214147
* R600/SI: Fix return type for isMIMG / isSMRDMatt Arsenault2014-07-281-2/+2
| | | | | | All the others use bool, so these should too. llvm-svn: 214106
* R600/SI: Add instruction shrinking passTom Stellard2014-07-211-0/+9
| | | | | | This pass converts 64-bit instructions to 32-bit when possible. llvm-svn: 213561
* R600/SI: Use scratch memory for large private arraysTom Stellard2014-07-211-1/+20
| | | | llvm-svn: 213551
* R600/SI: Store constant initializer data in constant memoryTom Stellard2014-07-211-0/+20
| | | | | | | | | | | | This implements a solution for constant initializers suggested by Vadim Girlin, where we store the data after the shader code and then use the S_GETPC instruction to compute its address. This saves use the trouble of creating a new buffer for constant data and then having to pass the pointer to the kernel via user SGPRs or the input buffer. llvm-svn: 213530
* R600/SI: Add verifier check for immediates in register operands.Tom Stellard2014-07-021-1/+8
| | | | llvm-svn: 212214
* R600/SI: Verify restrictions on div_scale operands.Matt Arsenault2014-06-231-0/+35
| | | | llvm-svn: 211524
* R600/SI: Add intrinsics for brev instructionsMatt Arsenault2014-06-181-0/+1
| | | | llvm-svn: 211187
* R600/SI: Match cttz_zero_undefMatt Arsenault2014-06-171-0/+1
| | | | llvm-svn: 211116
* R600/SI: Match ctlz_zero_undefMatt Arsenault2014-06-171-0/+1
| | | | llvm-svn: 211115
* R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtargetTom Stellard2014-06-131-3/+3
| | | | llvm-svn: 210869
* R600/SI: Emit an error when attempting to spill VGPRs v4Tom Stellard2014-06-101-10/+24
| | | | | | | | | | | | | | | | | | I can't get VGPR spilling to work reliable, so for now just emit an error when the register allocator tries to spill VGPRs. v2: - Fix build v3: - Added crash fix when spilling SPGRs v4: - Use V_MOV_B32 as a dummy instruction instead of S_NOP Patch by: Darren Powell https://bugs.freedesktop.org/show_bug.cgi?id=75276 llvm-svn: 210588
* R600/SI: Fix a crash when spilling SGPRsTom Stellard2014-06-101-11/+7
| | | | | | | | | | | We need to make sure only one new instruction is added when spilling otherwise the register allocator may crash. This fixes a crash in the game Antichamber. https://bugs.freedesktop.org/show_bug.cgi?id=75276 llvm-svn: 210587
* R600/SI: Implement i64 ctpopMatt Arsenault2014-06-101-0/+45
| | | | llvm-svn: 210568
* R600/SI: Use bcnt instruction for ctpopMatt Arsenault2014-06-101-0/+5
| | | | llvm-svn: 210567
* R600/SI: Keep 64-bit not on SALUMatt Arsenault2014-06-091-7/+61
| | | | llvm-svn: 210476
* Fix typosMatt Arsenault2014-06-031-2/+2
| | | | llvm-svn: 210135
* R600/SI: Fix a bug with handling of INSERT_SUBREG in SIFixSGPRCopiesTom Stellard2014-05-151-0/+18
| | | | | | This prevents a future commit from regressing the load-i1.ll test. llvm-svn: 208887
* R600/SI: Try to fix BFE operands when moving to VALUMatt Arsenault2014-05-131-1/+1
| | | | | | This was broken by r208479 llvm-svn: 208740
* R600/SI: Prettier display of input modifiersVincent Lejeune2014-05-101-4/+7
| | | | llvm-svn: 208479
* R600/SI: Teach SIInstrInfo::moveToVALU() how to move S_LOAD_*_IMM instructionsTom Stellard2014-05-091-4/+35
| | | | llvm-svn: 208432
* R600/SI: Only create one instruction when spilling/restoring register v3Tom Stellard2014-05-021-25/+138
| | | | | | | | | | | | | | | | | | The register spiller assumes that only one new instruction is created when spilling and restoring registers, so we need to emit pseudo instructions for vector register spills and lower them after register allocation. v2: - Fix calculation of lane index - Extend VGPR liveness to end of program. v3: - Use SIMM16 field of S_NOP to specify multiple NOPs. https://bugs.freedesktop.org/show_bug.cgi?id=75005 llvm-svn: 207843
* R600/SI: Teach moveToVALU how to handle some SMRD instructionsTom Stellard2014-04-301-1/+47
| | | | llvm-svn: 207660
* [C++] Use 'nullptr'. Target edition.Craig Topper2014-04-251-5/+5
| | | | llvm-svn: 207197
* R600/SI: Try to use scalar BFE.Matt Arsenault2014-04-181-0/+23
| | | | | | | | Use scalar BFE with constant shift and offset when possible. This is complicated by the fact that the scalar version packs the two operands of the vector version into one. llvm-svn: 206558
* R600/SI: Match sign_extend_inreg to s_sext_i32_i8 and s_sext_i32_i16Matt Arsenault2014-04-181-14/+38
| | | | llvm-svn: 206547
* R600/SI: Teach SIInstrInfo::moveToVALU() how to handle PHI instructionsTom Stellard2014-04-171-3/+15
| | | | llvm-svn: 206498
* R600/SI: Legalize operands after changing dst reg in FixSGPRCopiesTom Stellard2014-04-171-2/+4
| | | | | | Otherwise we may not legalize some illegal REG_SEQUENCE instructions. llvm-svn: 206497
* R600/SI: Refactor SOPC classes slightly.Matt Arsenault2014-04-111-0/+6
| | | | | | | Better match what is done for VOPC to eventually prefer selecting these. llvm-svn: 206048
* R600/SI: Match not instruction.Matt Arsenault2014-04-091-0/+1
| | | | llvm-svn: 205837
* R600/SI: Handle INSERT_SUBREG in SIFixSGPRCopiesTom Stellard2014-04-071-0/+2
| | | | llvm-svn: 205732
* R600/SI: Implement shouldConvertConstantLoadToIntImmMatt Arsenault2014-03-311-18/+26
| | | | llvm-svn: 205244
* R600/SI: Implement SIInstrInfo::isTriviallyRematerializable()Tom Stellard2014-03-311-0/+12
| | | | llvm-svn: 205188
* R600/SI: Fix extra mov from legalizing 64-bit SALU ops.Matt Arsenault2014-03-241-14/+26
| | | | | | | Check the register class of each operand individually to avoid an extra copy to a vgpr. llvm-svn: 204662
* R600/SI: Sub-optimial fix for 64-bit immediates with SALU ops.Matt Arsenault2014-03-241-16/+37
| | | | | | | No longer asserts, but now you get moves loading legal immediates into the split 32-bit operations. llvm-svn: 204661
* R600/SI: Fix 64-bit bit ops that require the VALU.Matt Arsenault2014-03-241-0/+76
| | | | | | | | Try to match scalar and first like the other instructions. Expand 64-bit ands to a pair of 32-bit ands since that is not available on the VALU. llvm-svn: 204660
* R600/SI: Move splitting 64-bit immediates to separate function.Matt Arsenault2014-03-241-39/+53
| | | | llvm-svn: 204651
* R600/SI: Fix warning with gcc 4.8.2Tom Stellard2014-03-241-1/+1
| | | | llvm-svn: 204618
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