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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-06-10 19:18:21 +0000 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2014-06-10 19:18:21 +0000 |
| commit | b5b5110b5c2be363f35a2ae90a9793cefb656dbf (patch) | |
| tree | ac6325c4fc02bab000c3cfbdd4aa9bcc5955b154 /llvm/lib/Target/R600/SIInstrInfo.cpp | |
| parent | 9a54da08e001dedd16e96def9c9ea1b413d838db (diff) | |
| download | bcm5719-llvm-b5b5110b5c2be363f35a2ae90a9793cefb656dbf.tar.gz bcm5719-llvm-b5b5110b5c2be363f35a2ae90a9793cefb656dbf.zip | |
R600/SI: Use bcnt instruction for ctpop
llvm-svn: 210567
Diffstat (limited to 'llvm/lib/Target/R600/SIInstrInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/R600/SIInstrInfo.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/R600/SIInstrInfo.cpp b/llvm/lib/Target/R600/SIInstrInfo.cpp index dc964349191..fdebb2ffb4d 100644 --- a/llvm/lib/Target/R600/SIInstrInfo.cpp +++ b/llvm/lib/Target/R600/SIInstrInfo.cpp @@ -668,6 +668,7 @@ unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) { case AMDGPU::S_LOAD_DWORDX2_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64; case AMDGPU::S_LOAD_DWORDX4_IMM: case AMDGPU::S_LOAD_DWORDX4_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64; + case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e32; } } @@ -1218,6 +1219,10 @@ void SIInstrInfo::moveToVALU(MachineInstr &TopInst) const { // 3 to not hit an assertion later in MCInstLower. Inst->addOperand(MachineOperand::CreateImm(0)); Inst->addOperand(MachineOperand::CreateImm(0)); + } else if (Opcode == AMDGPU::S_BCNT1_I32_B32) { + // The VALU version adds the second operand to the result, so insert an + // extra 0 operand. + Inst->addOperand(MachineOperand::CreateImm(0)); } addDescImplicitUseDef(NewDesc, Inst); |

